Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2008-01-29
2008-01-29
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S111000, C711S156000
Reexamination Certificate
active
11250488
ABSTRACT:
A controller existing on a level above a media drive issues a first read command specifying a plurality of data blocks to the media drive, and upon detecting a time-out for the first read command, generates a second read command specifying a portion of the data blocks among the plurality of data blocks, and issues the second read command to the media drive. Upon receiving the portion of data blocks without detecting a time-out for the second read command, the controller reads the plurality of data blocks specified by the first read command by issuing the second read command to the media drive one or more times.
REFERENCES:
patent: 6049891 (2000-04-01), Inamoto
patent: 6799283 (2004-09-01), Tamai et al.
patent: 7149846 (2006-12-01), Hetrick
patent: 2004/0236908 (2004-11-01), Suzuki et al.
Iwamitsu Koji
Uchiyama Yoshihiro
Bragdon Reginald
Vo Thanh D
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