Storage subsystem including an error correcting cache and means

Details Storage subsystem including an error correcting cache and means Storage subsystem including an error correcting cache and means

1999-04-14

2000-12-12

Lane, Jack A.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714800, 714805, 711118, G11C 1100

Patent

active

061612081

ABSTRACT:
A storage subsystem for use in a data processing system having real and extended storage, a vector processor and a store-in cache buffer. Transfers between real and extended storage are performed with a store buffer external to the cache, but comparable in size to the line size of the cache directly associated with the real storage. Hard data errors in the cache are corrected with hardware invert-retry mechanism which operates in response to a machine check and does the correction as a part of the instruction retry. Vector processor storage operations bypass the cache and transfer data directly from storage to the vector processor.

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IBM Technical Disclosure Bulletin, vol. 15, No. 2, Jul. 1972, p. 503, New York, U.S.; K. Helwig et al, "Error Correction Without Use of Error-Correction Code".
Thirty-Second IEEE Computer Society International Conference, San Francisco, CA, 23rd-247th Feb., 1987, pp. 106-109, IEEE, New York, US: S. G. Tucker, "The IBM 3090 System Design with Emphasis on the Vector Facility".

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