Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2007-07-03
2007-07-03
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S118000, C711S154000, C711S173000, C711S209000, C710S054000
Reexamination Certificate
active
11328057
ABSTRACT:
The present invention partitions a cache region of a storage subsystem for each user and prevents interference between user-dedicated regions.A plurality of CLPR can be established within the storage subsystem. A CLPR is a user-dedicated region that can be used by partitioning the cache region of a cache memory. Management information required to manage the data stored in the cache memory is allocated to each CLPR in accordance with the attribute of the segment or slot. The clean queue and clean counter, which manage the segments in a clean state, are provided in each CLPR. The dirty queue and dirty counter are used jointly by all the CLPR. The free queue, classification queue, and BIND queue are applied jointly to all the CLPR, only the counters being provided in each CLPR.
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Hoshino Sachiko
Nagasoe Yasuyuki
Sakaguchi Takashi
Sugino Shoji
Bataille Pierre-Michel
Hitachi , Ltd.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
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