Storage for generating ECC and adding ECC to data

Details Storage for generating ECC and adding ECC to data Storage for generating ECC and adding ECC to data

1998-09-29

2003-02-25

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

06526537

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to storage using a memory device having a continuous transfer function as typified by an SRAM (Synchronous Random Access Memory) or a DRAM (Dynamic RAM) with EDO (Extended Data Out). More particularly, the present invention is concerned with a storage including means for generating a single ECC (Error Correcting Code) particular to data error control technologies for N read/write units and controlling error correction/detection.
2. Description of the Related Art
Semiconductor memory devices typified by DRAMs have customarily been used in computers and peripherals thereof for storing programs and/or computation data as needed. To store accurate data in a semiconductor memory device, it is a common practice to use an ECC system adding a preselected number of check bits necessary for an ECC to data bits, writing them in the memory device together, and detecting or correcting, based on the data bits and check bits, errors with an error detecting circuit at the time of data reading. Also, the ratio of the number of check bits to the number of data bits should preferably be reduced from the standpoint of the amount of hardware, i.e., the number of memory devices. In light of this, an ECC system generally referred to as SEC-DED (Single-bit Error Correction Double-bits Error Detection) is predominant over the other ECC systems.
Today, in parallel with the progress of semiconductor technologies, the capacity of a memory device is increasing while even personal computers are required to have a huge storage capacity. However, the unit storage capacity to be extended should preferably be as small as possible from the market needs and product standpoint Moreover, a current trend is toward a DRAM having multiple bits, e.g., four bits or eight bits, as distinguished from a single bit, for reducing the space and cost to be allocated to the DRAM. Fast data transfer to a memory device is another prerequisite in consideration of the increasing operation speed of a processor. To meet this requirement, a DRAM or an SDRAM with EDO capable of transferring data at a higher speed than the conventional DRAM has recently been developed.
However, when the number of bits of the memory device is increased, the conventional SEC-DED ECC system cannot recover a single memory device from all faults It is therefore necessary to increase the number of check bits for remedying aft the faults of a plurality of bits or to physically spread data via software such that the faults of a plurality of bits do not overlap in a single ECC. The data spreading scheme is taught in Japanese Patent Laid-Open Publication No. 61-177559. However, the former scheme is not practicable without resorting to a prohibitive number of bits in the error correction theory aspect, resulting in an increase in hardware (number of memory devices) for storing data consisting of data bits and check bits.
Why the number of memory devices increases with an increase in the number of check bits (ECC) is as follows. A relation between the number of data bits and the number of check bits necessary for an ECC function, as determined by the ECC code theory, is as follows. Every condition shown below is well known in the art.
Number of
Number of
Item No.
Data Bits
Check Bits
ECC Function
1
32 bits
 7 bits
1 bit for error correction/2
bits for error detection
(SEC-DED)
2
64 bits
 8 bits
same as above
3
64 bits
12 bits
nearby 2 bits for error
correction/4 bits for error
detection (S2ED-D2ED)
4
128 bits 
16 bits
nearby 4 bits for error
correction/8 bits for error
detection (S4EC-D4ED)
As listed above, although the number of check bits necessary for implementing the same ECC function increases with an increase in the number of data bits, the ratio of the number of check bits to the number of data bits decreases (compare item Nos.
1
and
2
). Even when the number of data bits and the ECC correcting function are doubled or quadrupled, the number of check bits is less than double or quadruple, respectively. As a result, efficiency is improved with respect to the error detecting/correcting function (compare item Nos.
1
,
3
and
4
).
However, the above conventional technologies have the following problems left unsolved. To detect or correct the errors of a plurality of bits with an ECC, there must be increased the amount of hardware (number of memory devices) to be allocated to the check bits. Specifically, the detection/correction of the errors of a plurality of bits is not practicable without resorting to check bits, i.e., hardware (number of memory devices) great enough to accommodate such a number of check bits. On the other hand, when the physical spreading of data using software is used to detect the faults of a plurality of bits with SEC-DED, the transfer ability of the storage falls while the hardware of an error control circuit increases. This is because overhead occurs at the time of data transfer due to the intermediary of software and because exclusive hardware is necessary for the data to be spread.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a storage using an SDRAM, DRAM with. EDO or similar memory device having a continuous transfer function.
It is another object of the present invention to provide a storage capable of reducing, in the correction/detection of errors of data with an ECC, the ratio of check bits to data bits and thereby reducing the required number of memory devices as far as possible white remedying the fault of a single memory whose number of bits is increasing.
In accordance with the present invention, in a storage capable of generating an ECC for data and adding the ECC to the data to thereby form a read/write unit, an ECC is generated for each N of the data, equally divided into N ECC code parts and then respectively added to the N data to thereby constitute read/write units, The read/write units are continuously written and read out of N continuous addresses of a memory device.
Also, in accordance with the present invention, a storage capable of generating an ECC for data and adding the ECC to the data to thereby form a read/write unit includes a writing circuit for generating an ECC for N of write data received from a host, adding Nequally divided ECC code parts to the Nwrite data, respectively, to thereby form Nwrite units, and writing the N write units to N continuous addresses of a semiconductor memory device, respectively. A reading circuit gathers the Nequally divided ECC code parts contained in read data units read out of the N continuous addresses of the semiconductor memory device to thereby reconstruct the ECC, and corrects errors of the N read data units with the reconstructed ECC.


REFERENCES:
patent: RE30187 (1980-01-01), Hong et al.
patent: 4377862 (1983-03-01), Koford et al.
patent: 4486882 (1984-12-01), Piret et al.
patent: 4841513 (1989-06-01), Farhangi et al.
patent: 4884194 (1989-11-01), Krol et al.
patent: 4905242 (1990-02-01), Popp
patent: 5291498 (1994-03-01), Jackson et al.
patent: 5313624 (1994-05-01), Harriman et al.
patent: 5537423 (1996-07-01), Chen
patent: 5875477 (1999-02-01), Hasbun et al.
patent: 5896404 (1999-04-01), Kellogg et al.
patent: 6064639 (2000-05-01), Sako et al.
patent: 6070262 (2000-05-01), Kellogg et al.
patent: 6223247 (2001-04-01), Otsuka et al.
patent: 1 209 269 (1986-06-01), None
patent: 57-055455 (1982-04-01), None
patent: 55-1030146 A 55 (1982-04-01), None
patent: 55-100698 (1982-06-01), None
patent: 57-100698 (1982-06-01), None
patent: 61-177559 (1986-08-01), None
patent: 3-242745 (1991-10-01), None
patent: 03292525 (1991-12-01), None
patent: 04370579 (1992-12-01), None
patent: 97/01138 (1997-01-01), None
Kalter et al(A 50-ns 16-Mb DRAM with a 10-ns Data Rate And On-Chip ECC. IEEE, 1990).*
Schumacher(Memory Controller Design In VLSI. IEEE, 1989).*
Fieger et al(Transport Protocols Over Wireless Links. IEEE, 1997).*
Franaszec et al(On Variable Scope of Parity Protection In Disk Arrays. IEEE, 1997).

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