Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-02
2001-05-08
Williams, Alexander O. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S310000, C438S253000, C438S254000, C438S396000
Reexamination Certificate
active
06229171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method for manufacturing the same and, more particularly, to a pillar type stacked storage node of a semiconductor capacity and a method for fabricating the same.
2. Description of the Related Art
As DRAM devices are scaled down to a line width of about a quarter micrometer, two-dimensional areas occupied by capacitors become smaller. On the other hand, since the capacitance of a capacitor must be maintained at a constant level, methods have been developed to maintain a desired capacitance from decreased two-dimensional areas.
One approach is to form a capacitor that has a three-dimensional structure by increasing the height of the capacitor so as to increase available cell surface areas. The increase in the height of the capacitor, however, causes a large step between the cell array region and the peripheral region, thus making it difficult to form metal interconnections.
An alternative approach is to increase the dielectric constant of the dielectric film of the capacitor. Recently, high dielectric materials such as strontium titanate (SrTiO
3
), barium-strontium titanate ((Ba—Sr)TiO
3
), or the like having dielectric constant of more than 10,000, have been adopted for use as dielectric films. However, when polysilicon is used as a capacitor storage node, a layer of low dielectric characteristic is formed at the interface between the polysilicon layer and the high dielectric film, which thereby increases leakage current of the dielectric film.
Transition metals such as platinum (Pt) or the like are preferably used as a capacitor storage node when a high dielectric material, such as strontium titanate or barium-strontium titanate, is used as a dielectric film. However, there are also some problems when such transition metals are used in a high integrated circuit device. For example, in application, to about the range of 0.1 to 0.2 micrometers of spaced apart storage nodes, etched transition metal may be left deposited on sidewalls of the patterned storage nodes during a dry-etch process. As a result, an electrical bridge, i.e., a short, can arise between adjacent storage nodes.
A reference article, entitled “A Stacked Capacitor With An MOCVD (Ba—Sr)TiO
3
Film And A RuO
2
/Ru Storage Node On A TiN-capped Plug For 4Gbit DRAMs And Beyond,” by H. Yamaguchi et al, IEDM 1996-675 relates to stacked storage nodes.
FIG. 1
is a cross-sectional view showing a stacked storage node according to the above-identified reference. The stacked storage node is fabricated by forming a contact hole
15
in an insulating layer
14
on a semiconductor substrate
10
by EB (electron beam) lithography and RIE (reactive ion etching). A phosphorous doped polysilicon layer
16
, about 2000Å thick, is deposited in the contact hole
15
and on the insulating layer
14
. The polysilicon layer
16
is then etched back to create a recess about 1000Å from the top surface of the insulating layer
14
in the contact hole
15
. Titanium is then deposited and annealed by RTA in N
2
ambient to form a TiSix layer to reduce contact resistance. A 4000Å thick barrier metal layer
17
, such as a titanium nitride layer, is then deposited and planarized to form a storage contact plug
18
by chemical mechanical polishing. As for the storage node, a thick transition metal layer
19
, about 4500Å, (double layer of 500Å ruthenium and 4000Å ruthenium dioxide) is deposited by DC sputtering with a Ru metal target. Then the transition metal layer
19
is etched to form the storage node
20
with 0.15 micrometer spacings between nodes. A high dielectric film
21
is then deposited on the insulating layer
14
and the storage node
20
.
However, there are some problems with the above mentioned method. For example, it is very difficult to etch the transition metal layer with about 0.15 micrometer spacings between the nodes. As mentioned above, etched transition metal can be redeposited on sidewalls of the storage nodes during dry etch. As a result, a storage node may have a sloped sidewall profile, thus forming an electrical bridge between adjacent storage nodes.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming, or at least reducing, the effects of the problems set forth above. In accordance with one aspect of the invention there is provided a stacked capacitor node comprising a thick polysilicon layer, a barrier metal layer and a thin transition metal layer with a high capacitance and a good lateral profile.
In accordance with another aspect of the invention there is provided a method for fabricating a stacked capacitor node that provides a high capacitance and a good lateral profile without electrical bridges between adjacent storage nodes.
The present invention provides a stacked storage node with a bottom polysilicon layer, a barrier metal layer/sidewall spacers, and a transition metal layer/sidewall spacers with a substantially vertical sidewall profile. The barrier metal layer is made of a material selected from the group consisting of TiAlN, TiSiN, TaTiN, and TaAlN. The transition metal layer is made of a material selected from the group consisting of Pt, Ir, Ru, and the like. The barrier metal layer/sidewall spacers prevent reaction between the polysilicon and the transition metal. Also, the barrier metal layer/sidewall spacers prevent the reaction between the polysilicon layer and high dielectric film together with the transistor metal/sidewall spacers. The polysilicon layer is formed thick, for example, about 1000 Å to 6000 Å, in order to increase capacitance. The barrier metal layer is formed with a thickness enough to prevent reaction, e.g., a thickness of about 500 Å to 1000 Å. The transition metal is formed thin, e.g., about 450 Å to 500 Å, to avoid slope etching resulting from its thickness.
The structure of polysilicon/barrier metal/transition metal electrode of a storage node in accordance with the present invention is formed by forming a transistor on an active region of a semiconductor substrate. The active region is surrounded by an insulator, i.e., field oxide layer. An insulating layer is formed on the resulting structure. A contact hole is formed in the insulating layer to contact a desired active region. A conductive layer is deposited in the contact opening and on the insulating layer and then planarized to form a contact plug. A doped polysilicon layer is deposited on the contact plug and the insulating layer to a thickness of about 1000 Å to 6000 Å. A first barrier metal layer is then deposited on the polysilicon layer to protect the polysilicon layer during subsequent process in oxidation ambient to a thickness of about 500 Å to 1000 Å. A first transition metal layer is deposited thinly on the barrier metal layer to a thickness of about 450 Å to 500 Å. Selected portions of the first transition metal layer, the first barrier metal layer, and the polysilicon layer are sequentially etched to form a stacked storage node in contact with the contact plug.
To protect exposed sidewalls of the polysilicon layer, conductive spacers are formed on sidewalls of the stacked storage node. That is, a second barrier metal layer is deposited over the stacked storage node and then etched back to form barrier metal spacers on sidewalls of the stacked storage node. The barrier metal spacers prevent oxidation of the sidewall polysilicon. A second transition metal layer is then deposited on the barrier metal spacer and then etched back to form transition metal spacers on sidewalls of the stacked storage node. A high dielectric film is deposited on the insulating layer and the stacked storage node.
The transition metal is formed thin to avoid slope etching thereof. The available surface area of the storage nodes can be increased by adjusting the thickness of the polysilicon and barrier metal. Accordingly, high capacitance capacitors can be formed without micro bridges, i.e., e
Chun Yoon-Soo
Chung Tae-Young
Hwang Yoo-Sang
Samsung Electronic Co. Ltd.
The Law Offices of Eugene M. Lee,PLLC
Williams Alexander O.
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