Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
1999-02-19
2001-11-06
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C365S222000, C711S106000
Reexamination Certificate
active
06313844
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a storage device provided with a dynamic random access memory (DRAM) or other semiconductor memory which requires a refresh for memory retention, an image processing apparatus and method of the same, and a refresh controller for controlling the refresh of the semiconductor memory and a method of the same.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) systems and in amusement machines. Especially, along with the recent advances in image processing techniques, systems using three-dimensional computer graphics are rapidly spreading.
In three-dimensional computer graphics, the color value of each pixel is calculated at the time of deciding the color of each corresponding pixel. Then, rendering is performed for writing the calculated value to an address of a display buffer (frame buffer memory) corresponding to the pixel.
One of the rendering methods is polygon rendering. In this method, a three-dimensional model is expressed as a composite of triangular unit graphics (polygons). By drawing using the polygons as units, the colors of the pixels of the display screen are decided.
In the above system, an image signal (data) obtained by the graphic processing is written (drawn) in an image memory. Then the image signal is read and output on a display such as a cathode ray tube (CRT).
As the image memory, semiconductor memories, such as a DRAM, are generally used.
A DRAM is configured by using a plurality of memory cells for storing data by accumulating charges in capacitors. The charges accumulated in the capacitors in such memory cells are lost along with time, so it is necessary to regularly refresh (recharge) the capacitors in the memory cells in order to maintain the stored data.
Note that writing and reading of data are prohibited during a refresh.
Accordingly, when using a DRAM as an image memory, in order to prevent deterioration of the picture quality of the image on the display by a refresh operation, a predetermined number of refreshes are performed during a horizontal blanking interval and vertical blanking interval of the image signal.
Also, in such an image memory, the image signal is drawn (written) during a time when a refresh is not being performed in the horizontal blanking interval and the vertical blanking interval when displaying the image on the display. The image signal read from the image memory is output to the display during display intervals.
In this case, because a refresh is essential for maintaining the storage of the image signal in the image memory, a refresh is given priority over a write operation of an image signal within the horizontal blanking interval and the vertical blanking interval.
Turning now to the problem to be solved by the present invention, the load of writing an image signal to an image memory varies in accordance with the resolution of the image corresponding to the image signal and the contents of the image signal.
Accordingly, if a refresh of the image memory is performed at fixed time intervals as in the related art, both the refresh and the write operation of the image signal to the image memory cannot be carried out within a blanking interval. As explained above, the refresh is given priority. Therefore, there is a possibility that a part of the image signal will not be able to be written in the image memory. In this way, there is a problem of deterioration of the displayed image when the necessary image signal cannot be written in the image memory.
Also, if a refresh of the image memory is performed at fixed time intervals as in the related art, the load of the semiconductor memory becomes heaviest when the load of writing is the heaviest, so that the peak of the power consumption becomes high along with that. Here, it is necessary to use interconnections, circuit elements, etc. in the semiconductor memory which have large capacities commensurate with the peak of the power consumption. Therefore, there is the problem that the semiconductor memory becomes large in size.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a storage device which can improve the performance in accessing a semiconductor memory while suitably retaining stored data of the semiconductor memory by a refresh, an image processing apparatus and a method of the same, and a refresh controller and method of the same.
Another object of the present invention is provide a storage device, an image processing apparatus, and a refresh controller which lightens the load of the semiconductor memory along with a refresh and helps reduce the size of the semiconductor memory.
To attain the above objects, according to a first aspect of the present invention, there is provided a storage device comprising at least one semiconductor memory which requires a refresh to retain memory; a memory access circuit for accessing the semiconductor memory; a refresh operation control circuit for controlling the semiconductor memory so that an instructed number of refreshes are performed in a predetermined period; and a refresh number determining circuit for monitoring the load of the access of the memory access circuit with respect to the semiconductor memory, determining the number of refreshes performed in the predetermined period on the basis of the load, and instructing the determined number of refreshes to the control circuit.
Preferably, the semiconductor memory stores an image signal; the memory access circuit writes the image signal to the semiconductor memory in a blanking interval at the time of displaying an image according to the image signal read from the semiconductor; and the refresh number determining circuit monitors the load of writing of the image signal by the memory access circuit.
Preferably, the memory access circuit reads the image signal from the semiconductor outside the blanking interval.
Preferably, the refresh number determining circuit determines the number of refreshes to be performed in the predetermined period to be smaller along with an increase of the access load.
Alternatively, the refresh number determining circuit executes a predetermined program, controls the memory access circuit on the basis of the result of the execution of the program, and determines the access load on the basis of the program.
More preferably, the at least one semiconductor memory comprises at least a first semiconductor memory and a second semiconductor memory capable of being accessed at the same time and the memory access circuit writes an image signal in the first semiconductor memory in a first blanking interval and a first display interval for reading image data from the second semiconductor memory following the first blanking interval and writes an image signal to the second semiconductor memory in a second blanking interval and a second display interval for reading image data from the first semiconductor memory following the second blanking interval.
More preferably, the semiconductor memory is a line buffer memory, a frame buffer memory, or a dynamic random access memory (DRAM).
More preferably, the blanking interval is a horizontal blanking interval.
According to a second aspect of the invention, there is provided a refresh controller for controlling a refresh of a semiconductor memory which requires a refresh to retain memory, comprising a refresh control circuit for control so that the semiconductor memory a performs an instructed number of refreshes in a predetermined period and a refresh number determining circuit for monitoring the load of the access with respect to the semiconductor memory, determining the number of refreshes to be performed in the predetermined period on the basis of the load, and instructing the determined number to the refresh control circuit.
Preferably, when an image signal is stored in the semiconductor memory and image data is written in the semiconductor memory in a blanking interval at the time of displaying an image in accordance with the image signal read from the
Kananen Ronald P.
Rader Fishman & Grauer
Sony Corporation
Tung Kee M.
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