Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-05-09
2006-05-09
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
07043603
ABSTRACT:
A storage device control unit for performing data writing/reading to/from a storage device responding to requests coming from an information processor. The storage device control unit includes: a communications interface section for carrying out communications with the information processor; a storage device interface section for carrying out communications with the storage device; a cache memory section including first memory for storage of data coming and going between the information processor and the storage device; and a connection section for connecting all together the communications interface section, the storage device interface section, and the cache memory section for communications thereamong. The connection section is provided with second memory for storage of data same as the one stored in the first memory. With such a structure, the inner process of the storage device control unit can be effective.
REFERENCES:
patent: 5475859 (1995-12-01), Kamabayashi et al.
patent: 5689728 (1997-11-01), Sugimoto et al.
patent: 6038641 (2000-03-01), Zangenehpour
patent: 6275897 (2001-08-01), Bachmat
patent: 6314491 (2001-11-01), Freerksen
patent: 6385681 (2002-05-01), Fujimoto et al.
patent: 6470419 (2002-10-01), Take et al.
patent: 6647461 (2003-11-01), Fujimoto et al.
patent: 6751703 (2004-06-01), Chilton
patent: 6813655 (2004-11-01), Hosoya et al.
patent: 2001/0011325 (2001-08-01), Day, III et al.
patent: 2001/0049773 (2001-12-01), Bhavsar
patent: 2002/0078299 (2002-06-01), Chiou et al.
patent: 2003/0188104 (2003-10-01), Sullivan
patent: 2004/0019740 (2004-01-01), Nakayama et al.
patent: 2004/0059870 (2004-03-01), Ash et al.
patent: 2004/0083338 (2004-04-01), Moriwaki et al.
patent: 0 671 691 (1995-02-01), None
patent: 0 800 137 (1997-03-01), None
patent: 0 845 738 (1997-11-01), None
patent: 2 271 653 (1993-10-01), None
patent: 2 366 424 (2001-03-01), None
patent: 2000-99281 (1998-09-01), None
United Kingdom Search Report dated Aug. 6, 2004.
English translation of French Search Report mailed Oct. 25, 2004.
Luiz Andrė Barroso, Lourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Sbaz Qadeer, Barton Sano, Scott Smith, Robert Stets and Ben Verghese, “Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing,” Proceedings of the 27thInternational Symposium on Computer Architecture, Jun. 13-14, 2000, pp. 282-293.
Ken Wood, “Built to Scale: The Hitachi Freedom Storage™ Lightning 9900™ Series,” Hitachi Data Systems-Enterprise Storage, Oct. 2000, pp. 1-18.
A. Marquez, Esq. Juan Carlos
Ellis Kevin L.
Fisher Esq. Stanley P.
Hitachi , Ltd.
Reed Smith LLP
LandOfFree
Storage device control unit and method of controlling the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Storage device control unit and method of controlling the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Storage device control unit and method of controlling the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3611566