Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2001-11-13
2002-10-29
Mai, Son (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S156000, C257S903000
Reexamination Certificate
active
06473333
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a storage circuit and a semiconductor memory device.
BACKGROUND ART
At present, as typical large-capacity semiconductor memory devices, a DRAM (Dynamic Random Access Memory) and a flash memory are named. In future, when pursuing further minuteness, and when trying to achieve reduction of bit cost and high performance, there are problems to be solved in each of these aspects. As regards further minuteness of the DRAM, a problem exists in measures for the structure of a capacity section, which results from the fact that the current DRAM adopts a cell structure of one transistor—one capacitor. To be more specific, the problem relates to the measures for the so-called stacked structure, in which for example, a capacity section is laminated on a substrate.
At present, the flash memory also has a problem of compatibility between minuteness and a life of a data storage period. Under the present circumstances, the flash memory is being developed with both of them as a backdrop. More specifically, the flash memory has the following principles of operation: during a write period, Fowler-Nordheim (FN)electric current is fed by means of a tunnel effect, or electric current is fed through an oxide film by a hot electron. Therefore, the electric current degrades the oxide flim, which places a limit on the number of times writing is allowed. In addition, it is not possible to scale the thickness of the oxide film in order to hold data. For these reasons, as described above, there is the problem of compatibility between minuteness and the life of a data storage period. Moreover, because the flash memory uses the same oxide film both for writing data and for data storage, the flash memory has also the disadvatage of compatibility between writing speed and a period during which data is held. Therefore, if the flash memory is used as a non-volatile memory, writing speed acnnot be increased under the present circumstances.
As a memory structure for solving the problems of the current large-capacity semiconductor memory, a PLED (Planar Localised Electron Device) is proposed. This can be found in, for example, reports at a symposium about VLSI technology in 1998, or the Japanese publication of patent applications (Japanese Patent Application Laid-Open No. Hei 10-200001, etc.). To be more specific, the examples at the symposium are the following: K. Nakazato et al., “PLED-Planar Localised Electron Devices”, IEDM Tech. Dig., pp. 179-182, 1997; H. Mizuta et al., “Normally-off PLED (planar Localised Electron Device) for non-volatile memory,” Symposium on VLSI Technology Tech. Dig. 1998.
In the documents named above, a PLED element is integrated as a layered structure on a transistor, which is produced on a silicon substrate. Using this as a gain cell solves the problem of complication of DRAM cell capacity. In addition, the documents also describe the following: as a layered structure, separating a storage node from a pn junction enables dramatic reduction of leak electric current at the junction; because of it, application as a non-volatile memory such as the flash memory becomes possible.
As above, the large-capacity semiconductor memory was described. In the field where high speed is required, a SRAM, in which six transistors constitute a cell, is generally used. A requirement for a non-volatile memory used for mobile apparatuses is high. However, as regards the conventional SRAM cell, in order to use the SRAM cell as a non-volatile memory, a combination of the SRAM cell with a battery backup is forced, which requires power consumption caused by leak electric current of a memory and a peripheral circuit.
DISCLOSURE OF INVENTION
An object of the present invention is to solve the problems of the prior art, and to provide a storage circuit or a flip-flop circuit, which has low power consumption, is non-volatile, and is high-speed. The present invention provides a SRAM cell that is low power consumption, non-volatile, and high-speed.
According to the present invention, it is possible to provide a low power consumption SRAM cell or a low power consumption flip-flop circuit, which is not provided by the prior art.
Moreover, another object of the present invention is to provide a non-volatile flip-flop that uses a low leak device as typified by the PLED element. Thus, in a state in which the power is supplied, having a node, which outputs stored information steadily, enables some circuit setting, and enables application as a Content Addressable Memory, etc.
A basic configuration according to the present invention is a storage circuit characterized by the following: said storage circuit has a semiconductor storage element, of which a memory node becomes low leakage, in a memory area; and said storage circuit has a second node, to which information stored in the first node is outputted steadily in a state in which power is supplied. In this case, the semiconductor storage element, of which a memory node is low leakage, means that a semiconductor storage element in which an interval of a holding operation of required storage information is long. If the interval of the holding operation of required storage information is, for example, one second or more (preferably, 10 seconds or more), it is suitable as the low leak semiconductor storage element according to the present invention. Moreover, if the interval of the holding operation of required storage information is about once a day or more, or about once a week or more, it is needless to say that the element is more desirable.
One specific configuration example of the present invention is a storage circuit characterized by the following:
a storage element is a device comprising:
a first path for a carrier;
a first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to a given voltage so that the second carrier is stored in the first node; and
said storage circuit comprises a second node, to which information stored in the first node is output steadily in a state in which power is supplied.
According to the storage circuit, it is possible to provide a non-volatile flip-flop circuit, which is capable of holding stored information even when the power supply is turned off. Moreover, according to the storage circuit, it is possible to provide a non-volatile SRAM (Static Random Access Memory), which is capable of holding stored information even when the power supply is turned off.
For purposes of providing the SRAM, it is desirable to configure a circuit according to the invention concepts, which will be described below. To be more specified, in the example, the low leak semiconductor element is built into a flip-flop; and a switch of the low leak semiconductor storage element is provided between a gate electrode of a drive transistor of the flip-flop and an output in phase with the gate electrode. Then, while writing and while data is being stored, the switch is turned ON or OFF. Thus, while writing data, an operation similar to that of the general SRAM is performed. In addition to it, while data is being stored, nonvolatility can also be achieve by shutting down the power supply.
A typical example of the semiconductor element for a switch, in which electric current is low leakage, is commonly called a PLED element. This PLED element is a semiconductor element comprising a layered structure of an insulated layer and a semiconductor layer, said semiconductor element is characterized by the following: the layered structure is placed between a first electrode and an electron storage node; and the layered structure controls electric current. As described above, this element itself can be found in, for example, the Japanese publication of patent applications (Japanese Patent Application Laid-Open No. Hei 10-200001).
In this case, in comparison with the present invention, the prior art will be considered as below. In general, the flip-flop circuit has a node that outputs stored information stea
Ishii Tomoyuki
Itoh Kiyoo
Sasaki Katsuro
Tachibana Suguru
Hitachi , Ltd.
Mai Son
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