Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
1999-09-22
2003-05-13
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S653000, C345S654000, C345S656000
Reexamination Certificate
active
06563507
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a storage circuit control device and the method thereof, and a graphic computation device and the method thereof, capable of simultaneously processing image data for multiple pixels, and moreover efficiently using the storage area of the storage circuit.
2. Description of the Related Art
Computer graphics are often used in various CAD (Computer Aided Design) systems, amusement devices, and so forth. Particularly, recent advancements in image processing technology has given rise to rapid propagation of systems using three-dimensional computer graphics.
With such three-dimensional computer graphics, rendering processing is performed in order to display the graphics on a display such as a CRT (Cathode Ray Tube) having pixels arrayed in matrix fashion.
In this rendering processing, the color data for each pixel is calculated, and the obtained color data is written to a display buffer (frame buffer) corresponding with the pixel. One of the techniques for rendering processing is polygon rendering. With this technique, a three-dimensional model is expressed as a combination of triangular unit shapes (polygons), and drawing is performed in units of these polygons, thereby determining the color of the display screen.
With three-dimensional computer graphics systems using such polygon rendering, texture mapping processing is performed at the time of drawing. This texture mapping processing reads texture data indicating an image pattern from a texture buffer in units of triangles, and pasts this read texture data onto the surface of the three-dimensional model, so as to obtain highly realistic image data.
With the texture mapping processing, as shown below, a two-dimensional texture address for specifying a pixel projecting an image according to the image data is calculated, and this is used as a texture address to make reference to texture data stored in the texture buffer.
Specifically, first, the (s, t, q) of each pixel within the triangle is calculated from linear interpolation, based on the (s
1
, t
1
, q
1
), (s
2
, t
2
, q
2
), and (s
3
, t
3
, q
3
) indicating the homogeneous coordinates (s, t) of the apexes of the triangle and the homogeneous item q.
Now, in simple terms, the homogeneous item q is the ratio of enlargement or reduction.
Next, division yields the (s/q, t/q) for each pixel, the s/q and t/q are each multiplied by the texture size USIZE and VSIZE, thereby generating texture coordinates data (u, v).
Next, the texture coordinates data (u, v) is converted into a texture address (U, V) on the texture buffer, and this texture address (U, V) is used to read the texture data from the texture buffer.
With three-dimensional computer graphics systems such as described above, the texture data may be stored in a two-dimensional array corresponding to a U and V coordinates system in the storage area of the texture buffer, so that direct reference can be made to the texture buffer using the texture address (U, V). That is to say, the two-dimensional texture address (U, V) may be directly used to access texture data stored in the texture buffer. This method simplifies the processing for accessing the texture data.
However, there is a problem with this method, in that storing multiple types of texture data in the texture buffer results in available area which cannot be efficiently used as shown in
FIG. 12
, due to the relation between the size of the texture data to be stored and the size of the available area, and consequently the storage area cannot be efficiently used.
For example, as shown in
FIG. 12
, in the event of storing pieces of texture data
400
,
401
,
402
,
403
, and
406
, each with differing address lengths in the U and V directions, within the address space of the texture buffer so that direct reference can be made with the texture address (U, V), available areas
410
and
411
where texture data cannot be stored is created due to the relation between the two-dimensional size of the texture data to be stored and the two-dimensional size of the available area.
Consequently, a texture buffer having an extremely great storage capacity in comparison to the amount of texture data to be stored must be used, increasing the scale of the system and raising costs.
Accordingly, conventional systems calculate a one-dimensional physical address A from a two-dimensional address (U, V), based on “physical address A=V×(texture width)+U”, and use this physical address A to access the texture buffer, in order to use the storage area of the texture buffer in an efficient manner. Thus, texture data can be stored without creating an available area in the storage area of the texture buffer, as shown in FIG.
13
.
Incidentally, “texture width” refers to the address length in the U direction, in the address space of the texture buffer.
FIG. 14
is a partial configuration diagram of a conventional three-dimensional computer graphic system.
As shown in
FIG. 14
, the physical address A for each pixel is calculated from the (s
1
, t
1
, q
1
), (s
2
, t
2
, q
2
), and (s
3
, t
3
, q
3
) of the apex of the triangle as described above, in the address converting device
104
built into the texture mapping device
101
. Then, using this calculated physical address A, the texture data (R, G, B, &agr;) is read from the texture buffer
102
to the texture mapping device
101
, this texture data (R, G, B, &agr;) is pasted to the pixels corresponding to the surface of the three-dimensional model, thereby generating plotting data S
101
. This plotting data S
101
is written to the display buffer
103
.
Also, with high-speed three-dimensional computer graphics systems, as shown in
FIG. 15
for example, an n number of texture mapping devices
101
1
through
101
n
each having built-in address converting devices
104
1
through
104
n
, and texture mapping processing is simultaneously performed for an n number of pixels in a parallel manner, thereby simultaneously writing the plotting data S
101
1
through S
101
n
to the display buffer.
Now, three-dimensional computer graphics systems such as described above may perform processing by simultaneously reading image data of pixels arrayed within a certain rectangle in a 2-by-2 or 4-by-4 matrix form.
However, using the physical address A generated by “physical address A=V×(texture width)+U” may make it difficult to guarantee that simultaneously read image data will be stored in different banks in the texture buffer.
Accordingly, with conventional three-dimensional computer graphics systems, access to the texture buffer regarding image data for simultaneous processing of multiple pixels has been made using two-dimensional texture addresses (U. V). Accordingly, as described above, there is the problem that the storage area of the texture buffer cannot be used efficiently.
SUMMARY OF THE INVENTION
The present invention has been made in light of the problems with the conventional art, and accordingly, it is an object of the present invention to provide a storage circuit control device and a graphic computation device capable of efficiently using the storage area of the texture buffer with a small circuit configuration, and moreover enabling simultaneous processing of image data for multiple pixels.
It is another object of the present invention to provide a storage circuit control method and a graphic computation method capable of efficiently using the storage area of the texture buffer, and moreover enabling simultaneous processing of image data for multiple pixels.
In order to solve the above-described problems with the conventional art, and to achieve the above objects, the storage circuit control device according to the present invention is a storage circuit control device which stores in a storage circuit two-dimensional image data including pixel data indicating the color of a plurality of pixels arrayed in matrix fashion, and simultaneously accesses the pixel data regarding the plurality of pixels stored in the storage circuit u
Bella Matthew C.
Fulwider Patton Lee & Utecht LLP
Monestime Mackly
LandOfFree
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