Storage circuit and method therefor

Details Storage circuit and method therefor Storage circuit and method therefor

2007-11-13

2007-11-13

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S189040, C365S190000, C365S063000

Reexamination Certificate

active

11132457

ABSTRACT:
Storage circuits (180-183and280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).

REFERENCES:
patent: 5854761 (1998-12-01), Patel et al.
patent: 6282143 (2001-08-01), Zhang et al.
patent: 6804143 (2004-10-01), Hobson
Morimura “A Shared-Bitline SRAM Cell Architecture for 1-V Ultra Low-Power Word-Bit Configurable Macrocells” NTT Lifestyle and Environmental Technology Laboratories; 1999; Kanagawa, Japan.

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