Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-10-12
2003-12-23
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S758000, C365S200000
Reexamination Certificate
active
06668341
ABSTRACT:
PRIOR FOREIGN APPLICATION
This application claims priority from European Patent Office Application No. 99122652.3, filed Nov. 13, 1999, which is hereby incorporated herein by reference in its entirety.
TECHNICAL FIELD
The present invention relates to electronic and microelectronic devices. In particular, the present invention relates to storage devices and in particular to storage cells, incorporated in computer systems which have some facility of error indication and error correction.
BACKGROUND ART
The present invention has a particular, preferred area in which it can be applied advantageously. This is memories of small capacity, in which control information, i.e. tags is stored for controlling the data flow in a program, or functional storage arrangements as, e.g., multi-port storage cells and content-adressable-memories (CAM).
Alpha particles and cosmic x-rays can disturb data which is stored in the above mentioned storage cells. When a bit value changes due to such occurrences, so-called soft errors have happened. In computer systems in which memory arrangements with an increased level of data security are incorporated, usually some kind of error detection is performed with the help of so called parity bits. In an enhanced form of data security management such soft errors are corrected with the help of so called error correctable codes (ECC). Such prior art technique is efficient only when it is applied portion-wise for large portions of data to be controlled, as e.g., 64 bits, or more. If the bit sequence to be error-controlled is small as it is the case with said tag bits, such ECC-method is not efficient anymore.
A different, second way which is often used for data security in tag bits is to double the data contained in the tag fields and compare it each time the data is read out. See for example in ‘Error-correcting Codes for Semiconductor Memory’, Chen, C. L., and Hsiao, M. Y., in IBM Journal of Research and Development, vol. 28, No. 2, March 1984. Both ways mentioned above are implementations which imply a data post-processing during which a program run has to be reset and continued with values which are not influenced by the wrong bit value implied by the above mentioned soft error. In modern processors in which a high degree of performance parallelization takes place such post-processing is a complicated and time-consuming work which decreases the overall computing performance.
Said second way to check for data integrity, i.e. to double the data, implies an increased area consumption on the respective chip, as will be described next below.
Error correctable codes add redundant bits, so called parity bits to the actual data bits. I.e. adding 8 ECC bits to a 64 bit word allows to correct a one bit failure and to detect up to two bit failures. An additional amount of 8 of 64 bits means a 12.5% increase in data to be stored and, further, it requires a special, dedicated logic for the generation and decoding of the ECC bits.
In memory devices, as e.g. on processor SRAM caches or main memory DRAM cells the increase of area consumption associated with the additional ECC bits is still tolerable because the area consumption of read and write access units required for accessing the storage cells in large arrays is relatively small compared to the large amount of area required for the data bits which are error-controlled.
For tag bits which are stored usually not in large arrays as e.g. the DRAM memory of a main memory chip but instead, in on processor SRAM arrays, the portion of area required for reading and writing circuits which access the data stored in the storing element of the respective storage cell is remarkably higher. This lies in the fact that only a small number of tag bits is usually stored. Thus, where doubling the tag bits, a 100% overhead plus an additional overhead for the error indication or error correction logic must be tolerated in prior art systems. This problem can be seen in FIG.
1
—a schematic illustration of a storage cell implementation—which is drawn only schematically, but which shows clearly the write
14
and read circuitry
16
comprising m+1, and n+1 input, or output lines, respectively with a respective write word line (WWL) or write bit line logic (WBL), or on the reading site—reading logic for word lines or bit lines (RWL, RBL). Such circuitry is required for writing or reading the bit value stored in the storing element
10
of the storage cell
As data security of tag bits is per se a must for guaranteeing a strong overall performance in a computer system such large area consumption implied by doubling the tag bits was tolerated in prior art systems. Nevertheless, the post-processing required for correcting the effect of a soft-error in consideration of speculative execution of error-affected code is time-consuming in a parallel processing computer system.
It is thus an object of the present invention to provide a storage cell which can be subjected to error indication methods and error correction methods without such a high overhead in area consumption as they are present in prior art storage cells.
It is a further object of the present invention to provide an improved storage cell which furthermore enhances the foregoing area savings and which is suited to extend this improvement for providing an ‘automatic’ error correction without any post-processing and without a further remarkable increase in area consumption compared to prior art implementations.
SUMMARY OF THE INVENTION
Said object of the invention is achieved by the features stated in enclosed independent claims. Further advantageous arrangements and embodiments of the invention are set forth in the respective subclaims.
The basic idea of the present invention is to double only the storing part inside the storing cell and share the environmental logic. Especially in case of multi-port cells this reduces the area penalty significantly because the read/write control within the cell is shared and only placed once.
According to a first preferred aspect of the present invention the storing elements in form of feedback latches should be advantageously designed in the layout in a way that a single alpha particle or cosmic x-ray cannot disturb both latch nodes. Writing the cell always writes both latches so that they hold the same data. A soft error can flip only one of the two latches. Then, a ‘XOR’ block detects that the data is no longer identical. While the data is read out the check bit indicates that the data is corrupted.
As the actual cell latch area is very small compared to the total area the duplication plus the additional ‘xor’ stage results in only 11% increase in area compared to a cell without duplication. The area advantage significantly increases with the number of ports shared.
According to a further advantageous aspect of the present invention the approach of doubling only the storing elements is extended to implement a triple storing element in the same cell. Then, with the help of a small and simple error correction logic in the cell from a ‘majority vote’ can be seen which bit value is wrong in case of a soft error affecting one bit in the cell. Thus the coinciding bit value is taken for true. Thus, an automatic bit control is provided in the storing cell itself. This is achieved with minimum expense of logic circuitry and space requirements. The particular advantage is that no post-processing is necessary after reading the bit from the cell, as it is true per se. Further, the advantages seen above are further enhanced.
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Krauch Ulrich
Mueller Antje
Pille Juergen
Wendel Dieter
Baderman Scott
Cutter, Esq. Lawrence D.
Heslin Rothenberg Farley & & Mesiti P.C.
Radigan, Esq. Kevin P.
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