Storage capacitor structure

Details Storage capacitor structure Storage capacitor structure

1997-05-14

2001-02-13

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C257S311000, C438S253000

Reexamination Certificate

active

06188099

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to a semiconductor device such as Dynamic Random Access Memory (hereinafter referred to as “DRAM”) into which a capacitor for accumulating charges as information can be readily formed and a method of manufacturing such a device.
2. Description of the Background Art
In recent years, there is a rapidly increasing demand for semiconductor devices with the remarkable spread of information equipments such as computer devices. From a functional view point, devices having larger storage capacity and capable of high speed operation are in demand. To cope with the demand, technological developments associated with semiconductor devices having higher integration density, faster response and higher reliability have been underway.
Among semiconductor memory devices, the DRAM permits random input/output of storage information. The DRAM generally includes a memory cell array, a storage region for accumulating a plurality of pieces of storage information, and peripheral circuitry necessary for input/output from/to the outside.
FIG. 11
is a block diagram showing the configuration of a general DRAM. Referring to
FIG. 11
, a DRAM
150
includes a memory cell array
151
for accumulating a data signal representing storage information, a row and column address buffer
152
for receiving an externally applied address signal to select a memory cell forming a unit storage circuit, a row decoder
153
and a column decoder
154
for designating the memory cell by decoding the address signal, a sense refresh amplifier
155
for amplifying and reading a signal accumulated in the designated memory cell, a data in buffer
156
and a data out buffer
157
for input/output of data, and a clock generator
158
for generating a clock signal. Memory cell array
151
occupying a large area on the semiconductor chip has a plurality of memory cells arranged in a matrix each accumulating unit storage information.
FIG. 12
is a diagram showing a circuit equivalent to memory cells for 4 bits in the memory cell array. Referring to
FIG. 12
, a memory cell includes a bit line
214
, an MOS (Metal-Oxide-Semiconductor) transistor
215
, a capacitor
216
having one electrode connected to MOS transistor
215
, and a word line
217
. Information is accumulated in capacitor
216
as charge. Each memory cell shown in
FIG. 12
is a so-called one-transistor-one-capacitor type memory cell formed of a single MOS transistor
215
and a single capacitor
216
connected thereto. The memory cell of this type is advantageous in increasing the integration density of the memory cell array for its simple structure, and is widely used in a DRAM which requires a large capacity.
Meanwhile, higher integration densities of semiconductor devices require a higher integration density of a memory cell array which requires a large area in a semiconductor device as well. In order to shrink the memory cell array, a capacitor forming part of a memory cell should be reduced in size as well. Reducing a capacitor in size however reduces the amount of charge as information to be accumulated in the capacitor (the amount of charge accumulated in a 1 bit memory cell).
If the amount of charge to be accumulated in a 1 bit memory cell is less than a fixed value, the operation of the DRAM as a storage device becomes unstable, resulting in lowered reliability. To this end, attempts to further increase the surface area of the electrode of a capacitor have been considered.
A semiconductor memory device and a manufacturing method thereof disclosed by Japanese Patent Laying-Open No. 6-310672 will be described by way of illustration.
FIG. 13
is a cross sectional view showing a memory cell in a DRAM disclosed by the document. Referring to
FIG. 13
, a pair of n
+
type diffusion layers
112
and
113
, the source/drain regions of an NMOS transistor are formed in a p type substrate
111
. A field oxide film
119
is formed to electrically isolate the NMOS transistor from another MOS transistor. Formed between the pair of n
+
type diffusion layers
112
and
113
on p substrate
111
is a gate (word line)
115
buried with a polysilicon film via a gate oxide film.
A lower capacitor electrode is formed of polysilicon films
132
and
133
, and polysilicon film
133
is electrically connected to n
+
type diffusion layer
112
. A polysilicon film
118
to form an upper capacitor electrode is formed on polysilicon film
133
with a thin film
117
having a large dielectric constant interposed therebetween. An insulating film
121
is formed on the substrate including the capacitor. A bit line
122
electrically connected to n
+
type diffusion layer
113
is formed.
In the memory cell as described above, the outer peripheral portion A of polysilicon film
133
which corresponds to the lower electrode of the capacitor and a side surface of a recess D formed in the vicinity of the center of polysilicon film
133
may further increase the surface area of the capacitor electrode. Thus, the capacity to accumulate charge in the capacitor is secured, and the operation of the DRAM may be stabilized.
Now, the semiconductor memory device as described above and a manufacturing method thereof will be described in conjunction with the accompanying drawings.
Referring to
FIG. 14
, field oxide film
119
, the pair of n
+
type diffusion layers
112
and
113
, and word line
115
functioning as a gate electrode are formed on p type substrate
111
. Then, an interlayer insulating film
114
of a silicon oxide film about as thick as 3000Å is formed by means of low pressure CVD. Referring to
FIG. 15
, a silicon nitride film
131
about as thick as 500Å is formed by means of low pressure CVD on interlayer insulating film
114
. Referring to
FIG. 16
, a polysilicon film
132
about as thick as 6000Å is formed on silicon nitride film
131
by means of low pressure CVD. Anisotropic etching is then performed to form a central hole C to expose a surface of silicon nitride film
131
.
Referring to
FIG. 17
, a silicon oxide film about as thick as 3000Å is formed on polysilicon film
132
including central hole C by means of atmospheric pressure CVD. The silicon oxide film is entirely etched back, and a side wall spacer
135
is formed only on the inner wall of central hole C.
Referring to
FIG. 18
, using side wall spacer
135
and polysilicon film
132
as a mask, a contact hole D is formed by a self-align contact process. Referring to
FIG. 19
, wet etching with hydrofluoric acid is performed to remove only the side wall spacer with silicon nitride film
131
remaining.
Referring to
FIG. 20
, polysilicon film
133
as thick as 500Å is formed on polysilicon film
132
by means of low pressure CVD. Then, polysilicon films
132
and
133
are subjected to anisotropic etching to form the lower electrode
116
of the capacitor in a prescribed shape.
Referring to
FIG. 13
, a silicon nitride film is formed on polysilicon film
133
by means of low pressure CVD. The silicon nitride film is oxidized to form thin film
117
having a large dielectric constant. Polysilicon film
118
to be the upper capacitor electrode is formed over thin film
117
. An insulating film
121
is formed to cover polysilicon film
118
. Bit line
122
is formed on insulating film
121
. Bit line
122
is electrically connected to n
+
type diffusion layer
113
. Through these steps, the memory cell in the DRAM is manufactured.
The document discloses that according to the method, contact hole
134
is provided by the self align contact process using as mask side wall spacer
135
and silicon nitride film
131
in the step shown in
FIG. 18
, and therefore contact hole
134
may be formed at an optimum position.
In recent semiconductor devices, however, even higher integration densities are in demand. To cope with the demand, forming a storage node to be the lower electrode of a capac

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