Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-11
2002-08-06
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S758000, C257S306000
Reexamination Certificate
active
06429474
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memories, and more particularly to structures and methods for forming interconnections within a semiconductor memory.
2. Description of the Prior Art
Generally speaking, there are two types of semiconductor memories. In the first type, data stored in the individual cell locations of the memory cannot be altered. Consequently, these memories are referred to as read-only memories. In the second type, data stored in each cell location can be altered, i.e., are subject to both read and write operations. The latter memories have therefore been called random-access memories.
Random-access memories (RAMs) come in various forms. Static random-access memories (SRAMs), for example, store data as long as they are connected to a power source. They also provide extremely rapid access, but at the cost of substantial power consumption, expense, and wafer space. Dynamic random access memories (DRAMs)use capacitive storage and thus must be re-written or refreshed on a periodic basis. They, however, are more economical and have improved storage density and power consumption requirements compared with SRAMs and thus their advantages have given engineers sufficient incentive to design around their drawbacks. DRAMs, therefore, remain the preferred choice of random-access memory for most chip designers.
Structurally speaking, a DRAM is formed from a plurality of memory cells arranged in the form of a matrix. Each cell includes a storage capacitor and a series-connected transistor, which is controlled by a word line running orthogonally to a pair of bit lines connected to a sense amplifier. To read data from the cell, the word line and sense amplifier are activated to cause the capacitor to output its charge to an associated one of a pair of bit lines. This charge causes a voltage imbalance to occur between the bit lines, which imbalance is amplified by the sense amplifier to a level representing a logical “0” or “1.” DRAMs of this type are disclosed, for example, in U.S. Pat. Nos. 5,012,447 and 5,416,734.
One effect which reduces the operational efficiency of a DRAM is noise which is capacitively coupled between adjacent bit lines. This noise, among other things, causes the sense amplifiers of the DRAM to output erroneous logic values. To reduce noise, it is common practice to cross (or “flip”) complementary bit lines at one or more locations along their length. Flipping bit lines in this manner reduces capacitive coupling and thus improves the overall accuracy of the memory. U.S. Pat. Nos. 5,550,769, 5,475,643, 5,214,601, 5,014,110, 5,012,447, and 4,980,860 disclose flipped bit-line DRAMs of this type.
DRAMs of the aforementioned type use dedicated wiring layers to form the flipped connections between their bit lines. Dedicated wiring layers are undesirable because they increase the cost and complexity of the fabrication process, as well as reduce integration density. Moreover, the storage capacitors in these DRAMs are often formed in layers beneath the bit lines, which further reduces integration density. U.S. Pat. Nos. 5,602,772 and 5,292,678 disclose DRAMs of this type.
Many conventional DRAMs, including those having flipped bit-lines, use stacked capacitors in their cells because of the increased electrode area and node capacitance they provide. The height of these capacitors, however, has proven troublesome because of the additional cost required in patterning their thick lower electrode, which further reduces integration density. The article, S. Sim et al. IEDM, 1996 discloses a conventional DRAM using stacked capacitors.
Attempts have been made to increase the integration density of a DRAM. U.S. Pat. No. 5,406,512 to Kagenishi, for example, proposes to form one electrode of a compensation capacitor from a portion of a bit line. The Kagenishi approach, however, actually decreases integration density because any improvement realized from using a bit line as a capacitor electrode is offset by the presence of compensation capacitors in the first place.
The Inventors of the present invention have recognized that space in the storage-capacitor-electrode level of a DRAM memory cell, for example, in a so-called support region (e.g. where support circuits such as decoders and sense amplifiers are located), has not been used for wiring or interconnection purposes. Using the support area in this manner, e.g., as an area in which connections to support circuits can be routed, would be particularly advantageous in improving the integration of a DRAM memory cell.
SUMMARY OF THE INVENTION
It is a first objective of the present invention to increase the integration density of a semiconductor memory device and simultaneously reduce its manufacturing costs.
It is second objective of the present invention to achieve the first objective by incorporating a wiring layer into an intermediate level of at least one memory cell of the semiconductor memory device and then using that wiring layer as a chip interconnect and/or any one of a variety of other purposes.
It is another objective of the present invention to form the aforementioned wiring layer in a level of a DRAM memory cell where at least one storage capacitor is located, and preferably in a support-circuit region within that level.
It is another objective of the present invention to form a DRAM memory cell having the aforementioned wiring layer, wherein the wiring layer includes at least one extra capacitor electrode formed at the storage-capacitor level of the cell.
It is another objective of the present invention to provide a DRAM memory cell of the aforementioned type, wherein the storage-capacitor level of the memory cell is located between chip interconnects and/or complementary bit lines of the DRAM, thereby increasing integration density compared with conventional DRAMs which use special, dedicated wiring levels to make these interconnections.
It is another objective of the present invention to form a DRAM memory cell of the aforementioned type in a region where bit lines of the DRAM are flipped, and then to use the capacitor electrode of the memory cell to establish a flip connection for at least one of the bit lines.
It is another objective of the present invention to provide a memory cell of the aforementioned type, wherein the capacitor electrode electrically connects one or more support circuits of the-DRAM.
It is another objective of the present invention to provide a method for making a DRAM memory cell of the aforementioned type, wherein the capacitor electrode is formed simultaneously with an electrode of at least one of the storage capacitors of the cell, thereby reducing the number of steps and the cost required to make the DRAM.
It is another objective of the present invention to provide a method for making a DRAM memory cell of the aforementioned type, wherein the capacitor electrode and the storage capacitor plates in the cell are made from a same conductive material.
These and other objects of the present invention are achieved by providing a DRAM memory cell having a first layer containing at least one transfer gate, a second layer including a first signal line, a third layer including second signal line, and an intermediate wiring layer between the first and second signal lines. The intermediate wiring layer includes an upper capacitor electrode and a lower capacitor electrode separated by a dielectric. Preferably, the capacitor electrodes are stacked capacitor electrodes made from platinum or iridium.
In one embodiment, the lower capacitor electrode connects the first and second signal lines through a hole formed in the upper capacitor electrode. In another embodiment, only the upper electrode connects the first and second signal lines. In still another embodiment, the lower electrode connects the first and second signal lines, while the upper electrode connects third and fourth signal lines.
The above embodiments are particularly well suited for locally-open globally-folded DRAM bit line architectures. The dual bit line
Bronner Gary B.
Gambino Jeffrey P.
Kotecki David E.
Radens Carl J.
Ho Hoai V.
Huynh Andy
Murray Susan M.
Whitham Curtis & Christofferson, P.C.
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