Storage architecture employing a transfer node to achieve...

Details Storage architecture employing a transfer node to achieve... Storage architecture employing a transfer node to achieve...

1999-11-09

2003-08-05

Gaffin, Jeffrey (Department: 2782)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S105000, C710S120000, C709S231000

Reexamination Certificate

active

06604155

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to data storage systems, and more particularly to data storage systems having a storage device controller interposed between a host computer and one or more data storage devices wherein the controller manages the storage of data within the one or more storage devices.
2. Description of the Related Art
Auxiliary storage devices such as magnetic or optical disk arrays are usually preferred for high-volume data storage. Many modern computer applications, such as high resolution video or graphic displays involving on-demand video servers, may heavily depend on the capacity of the host computer to perform in a data-intensive environment. In other words, necessity for external storage of data in relatively slower auxiliary data storage devices demands that the host computer system accomplish requisite data transfers at a rate that does not severely restrict the utility of the application that necessitated high-volume data transfers. Due to the speed differential between a host processor and an external storage device, a storage controller is almost invariably employed to manage data transfers to/from the host and from/to the storage device.
The purpose of a storage controller is to manage the storage for the host processor, leaving the higher speed host processor to perform other tasks during the time the storage controller accomplishes the requested data transfer to/from the external storage. The host generally performs simple data operations such as data reads and data writes. It is the duty of the storage controller to manage storage redundancy, hardware failure recovery, and volume organization for the data in the auxiliary storage. Redundant array of independent disks (RAID) algorithms are often used to manage data storage among a number of disk drives.
FIG. 1
is a diagram of a conventional computer system
10
including a host computer
12
coupled to a storage controller
14
by an interconnect link
16
, and two storage devices
18
A-
18
B coupled to storage controller
14
by respective interconnect links
20
A and
20
B. Each storage device
18
may be, for example, a disk drive array or a tape drive. Links
16
and
20
A-
20
B may include suitable interfaces for I/O data transfers (e.g., Fibre Channel, small computer system interface or SCSI, etc.) As evident in
FIG. 1
, all of the information involved in data transfers between host computer
12
and storage devices
18
A-
18
B passes through storage controller
14
. Storage controller
14
receives command, status, and data packets during the data transfer.
FIG. 2
is a diagram illustrating an exemplary flow of control and data packets during a data read operation initiated by host computer
12
of FIG.
1
. Links
16
and
20
A-
20
B in
FIG. 1
may be Fibre Channel links, and the data transfer protocol of
FIGS. 1 and 2
may be the Fibre Channel protocol. Referring to
FIGS. 1 and 2
together, host computer
12
issues a read command packet identifying storage controller
14
as its destination (XID=H,A) via link
16
. Storage controller
14
receives the read command and determines that two separate read operations are required to obtain the requested data; one from storage device
18
A and the other from storage device
18
B.
Storage controller
14
translates the read command from host computer
12
into two separate read commands, one read command for storage device
18
A and the other read command for storage device
18
B. Storage controller
14
transmits a first read command packet identifying storage device
18
A as its destination (XID=A,B) via link
20
A, and a second read command packet identifying storage device
18
B as its destination (XID=A,C) via link
20
B. Each read command packet instructs respective storage devices
18
A-
18
B to access and provide data identified by the read command. Storage device
18
A (ID=B) accesses the requested data and transmits a data packet followed by a status packet (XID=B,A) to storage controller
14
via link
20
A. Storage device
18
B (ID=C) accesses the requested data and transmits a data packet followed by a status packet (XID=C,A) to storage controller
14
via link
20
B. Each status packet may indicate whether the corresponding read operation was successful (i.e. whether the data read was valid).
Storage controller
14
typically includes a memory unit, and temporarily stores data and status packets in the memory unit. Storage controller
14
then consolidates the data received from storage devices
18
A-
18
B and processes the status packets received from storage devices
18
A-
18
B to form a composite status. Storage controller
14
transmits the consolidated data followed by the composite status (XID=A,H) to host computer
12
via link
16
, completing the read operation. In the event that the composite status indicates a read operation error, host computer
12
may ignore the consolidated data and initiate a new read operation. In general, the flow of packets depicted in
FIG. 2
is typical of a two-party point-to-point interface protocol (e.g., the Fibre Channel protocol).
As indicated in
FIG. 1
, storage controller
14
includes multiple communication ports. In addition to the memory and the multiple communication ports, storage controller
14
also typically includes one or more central processing units (CPUs). The multiple communication ports and the CPUs may be coupled to a communication bus. The CPUs and the memory may be coupled to a common bus within storage controller
14
, and the CPUs may access the memory via the bus.
Two parameters are commonly used to measure the performance of a storage system: (1) the number of input/output (I/O) operations per second (IOPS), and (2) the data transfer rate of the storage system. Generally, the rate of execution of I/O operations by a storage controller is governed by the type, speed and number of CPUs within the storage controller. The data transfer rate depends on the data transfer bandwidth of the storage controller. In computer system
10
described above, all of the data transferred between host computer
12
and storage devices
18
A-
18
B is temporarily stored within the memory of storage controller
14
, and thus travels through the bus of storage controller
14
. As a result, the data transfer bandwidth of storage controller
14
is largely dependent upon the bandwidth of the bus of storage controller
14
.
Current storage systems have restricted scalability because of the storage controllers having a relatively inflexible ratio of CPU to bandwidth capability. This is especially true if they are based on “off-the-shelf” microprocessors or computer systems. Usually the storage controller is designed to satisfy the majority of IOPS and data rate performance requirements with one implementation. This interdependence between IOPS and data transfer rate results in less efficient scalability of performance parameters. For example, in conventional storage controller architectures, an increase in data transfer rate may require both an increase in data transfer bandwidth and an increase in the number of CPUs residing within the controller.
It would thus be desirable to have a storage system wherein control functionality (as measured by the IOPS parameter) is scalable independently of the data transfer bandwidth (which determines the data transfer rate), and vice versa. It may be further desirable to achieve independence in scalability without necessitating a change in the existing communication protocol used within the storage system.
SUMMARY OF THE INVENTION
One embodiment of a transfer node is described, including a first channel port adapted for coupling to a host computer, a second channel port adapted for coupling to a storage controller and one or more storage devices, a central processing unit (CPU) coupled to the first and second channel ports, and a memory coupled to the CPU. The transfer node receives data routing information associated with a data transfer command

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