Storage and recovery of data based on change in MIS...

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S182000, C365S185080

Reexamination Certificate

active

07149104

ABSTRACT:
A memory circuit includes a latch having a first node and a second node, a word selecting line, a first MIS transistor having the source/drain nodes thereof coupled to the first node and a predetermined node, respectively, and the gate node thereof coupled to the word selecting line, a second MIS transistor having the source/drain nodes thereof coupled to the second node and the predetermined node, respectively, and the gate node thereof coupled to the word selecting line, and a control circuit configured to subject in a write mode, one of the first MIS transistor and the second MIS transistor to bias conditions that cause a lingering change in transistor characteristics thereof, and to subject in a recovery mode both the first MIS transistor and the second MIS transistor for equal amount of time to equal bias conditions that cause a lingering change in transistor characteristics thereof.

REFERENCES:
patent: 3636530 (1972-01-01), Mark et al.
patent: 4419744 (1983-12-01), Rutter
patent: 5956269 (1999-09-01), Ouyang et al.
patent: 6038168 (2000-03-01), Allen et al.
patent: 6466482 (2002-10-01), Shukuri et al.
patent: 6906953 (2005-06-01), Forbes
patent: 6906962 (2005-06-01), Layman et al.
patent: 6909635 (2005-06-01), Forbes et al.
patent: 2005/0232009 (2005-10-01), Nakamura
patent: 06 076582 (1994-03-01), None
patent: WO 2004 057621 (2004-07-01), None

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