Storage and addressing method for a buffer memory control system

Details Storage and addressing method for a buffer memory control system Storage and addressing method for a buffer memory control system

1995-12-19

1998-06-09

Swann, Tod R.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711167, G06F 1210

Patent

active

057652031

ABSTRACT:
A method of storing and retrieving P user information data and Q error information data for the P user information data in a buffer memory unit having multiple DRAMs. P user information data and Q error information data together define a paragraph. Each user information data and error information data have a plurality of information units. Each DRAM has a plurality of rows and columns, with a maximum column address of M and each row capable of storing N such paragraphs. The virtual memory address for each user information data is translated by dividing the virtual memory address by N, then assigning quotient of the division as the row address and assigning remainder of the division as the starting base column address for the user information data. To store or retrieve successive user information data within a paragraph, the base column address is incremented from (starting base column address+0) to (starting base column address+P). The method of selecting a column address for the error information data when the number of error information data per paragraph is one, includes the steps of subtracting starting base column address of corresponding user information data from M the maximum column address and assigning result as the column address for error information data.

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patent: 5280601 (1994-01-01), Desai et al.
patent: 5303364 (1994-04-01), Mayer et al.

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