Electrical computers and digital processing systems: memory – Address formation – Address multiplexing or address bus manipulation
Reexamination Certificate
2000-08-30
2004-01-27
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address multiplexing or address bus manipulation
C711S104000
Reexamination Certificate
active
06684316
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The invention concerns a storage access unit with an internal address bus that contains a pre-set number of internal address lines for transfer of an internal address word. The address word is produced by a processor, for example. The storage access unit contains moreover an internal data bus which contains several internal data lines for the transfer of an internal data word which is written or read by the processor. There is attached to an external address bus of the storage access unit the addressing connections of a static storage unit or the addressing connections of a dynamic storage unit, dependent on the selected mode of operation. The external address bus also contains a pre-set number of external address lines. The data connections of the storage unit are linked to an external data bus of the storage access unit. The external data bus contains a pre-set number of data lines for the transfer of data from or to the storage unit.
A control unit of the storage access unit controls dependent on the chosen mode of operation the passing on of an internal address data word along the external address bus as well as the data transfer between the internal data bus and external data bus.
A RAM (Random Access Memory) is a storage unit with which a person can store data after presentation of an address and read these again under this address, a so-called random access. There is a distinction made between static RAMs (SRAM static random access memory) and dynamic RAMs (DRAM—dynamic random access memory). In the case of static storage units, the storage content remains preserved without extra measures for so long as the operating voltage is applied. In the case of dynamic storage units, the storage content is refreshed by reading accessions which must be carried out at regular intervals so that the storage content is not lost.
It would be possible for the internal address bus to be linked with the external address bus for the operation of a static storage unit. Furthermore, the internal data bus could be linked up with the external data bus. For the operation of a dynamic storage unit there is used a so-called storage controller between an internal address bus and an external address bus, which creates from the internal address word an external line address word for addressing of a line of the storage unit and an external column address word for addressing a column of the storage unit.
As for known circuits with a storage access unit to which selectively a SRAM or DRAM can be connected, their internal design is unfamiliar. There are several possibilities for achieving this function. For every mode of operation it is possible to use its own interface unit, for example.
The invention has the task of offering a simply designed storage access unit for random access to a static storage unit or a dynamic storage unit. Furthermore, procedures are suggested which are carried out in the storage access unit.
This object is solved for a storage access unit by the features indicated in patent claim 1. Further developments are given in the sub-claims.
The invention proceeds from the consideration that it is desirable to give the customer the possibility of using in their appliance a static or dynamic storage unit dependent on market price shortly before the delivery of an appliance. The invention also proceeds from the consideration that it is desirable that a processor using the storage unit should work independently of the operational mode in exactly the same way.
Thus with the storage access unit according to the invention there is used an address register whose address connections are linked with the internal address bus and whose data connections are linked with the internal data bus. The address register serves to store the internal address word to be passed on to the storage unit which is used by the storage unit for access. Moreover, a data register is used with the procedure according to the invention whose address connections are linked with the internal address bus and the data connections to the internal data bus. The data register is used for the intermediate storage of a data word which is already transferred via the external data bus, i.e. read out from the storage unit, or still to be transferred from the external data bus, i.e. to be written into the storage unit. According to the procedure of the invention the processor, independently of the chosen operational mode, always only has access to the address register and data register. The control unit then evaluates the address word stored in the address register dependent on the chosen operational mode and has access to the storage unit. In the case of a write access the data word previously stored in the data register by the processor is given out in the external data bus. In the case of a read access a data word in the storage unit is read from the address given by the address word and written into the data register. From there it is then read out by the processor.
The processor is not in the position when using the storage access unit according to the invention to carry out a storage accession within one processor cycle. A processor cycle is determined by the time that is required for loading the so-called accumulator. In the storage access unit according to the invention the processor must first store an address value in the address register. For this, the address value must be transferred to the internal data bus. Only then can access to the data register ensue. This is however not a disadvantage if the storage access unit is used for an application in which there is sufficient time available for storage access, for example the read-out of a teletext page.
Instruction sequences for the processor can be programmed independently of the storage unit connected later to the storage access unit. This saves expenditure of effort on development. As there is lastly only one instruction sequence for both storage units, storage space for storing the instruction sequence is also spared.
In one development of the storage access unit according to the invention a first data register is used whose address is present on the internal address bus upon writing of an internal data word. The address of a second data register diverges from the address of the first data register. The second data register is addressed on reading an internal data word via the internal address bus. By means of these measures the result is achieved that by addressing the data register it is already determined whether a writing or a reading process is to be carried out, which are dealt with in a different way respectively by the control unit. An assessment of the connection for selecting of a writing or reading operation on the processor may be omitted.
In one embodiment the control unit, when writing a data word into the data register, writes this data word automatically into the storage unit at the address stored in the address register. On reading the second data register the control unit automatically reads a data word from the storage unit which is stored at the address stored in the address register. The data word read out is then stored in the second data register. After access to the data register, access is started automatically to the storage unit, without additional signalling being required.
This leads to shorter access times. If when writing the address register, a data word is read automatically by the control unit from the storage unit, it can thus be achieved that in the case of a subsequent reading access to the data register, the data word stored in the address which is stored in the address register in the storage unit is already stored there. A further reading access to the second data register may be omitted.
The second reading access to the second data register leads to a non-essential extension of the storage access time, if several successive addresses of the storage unit are read. In such a case, the data words are carried over with a delay of one reading cycle of the second data register to the processor.
Himmel Thomas
Jünke Manfred
Rohrer Stefan
Harness & Dickey & Pierce P.L.C.
Micronas GmbH
Moazzami Nasser
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