Stop clock throttling in a computer processor through disabling

Details Stop clock throttling in a computer processor through disabling Stop clock throttling in a computer processor through disabling

1996-12-19

2000-09-26

Shenkh, Ayaz R.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

713320, 713322, 713324, G06F 126

Patent

active

061254509

ABSTRACT:
Microprocessors are often used in portable equipment that run on battery power. Thus, microprocessors used in such environments should save power when ever possible. Processors that have internal cache memories and allow external bus masters present a difficult case. Such processor's cannot enter a low power state since an external bus master may attempt to access a memory location that is represented in the internal cache. The present invention introduces a method and apparatus for allowing a processor having an internal cache to enter a low power state even though there may be other bus masters. A bus idle timer or an operating system monitors the bus to determine if the system bus is idle. When the system bus is idle, a bus arbiter is disabled to prevent bus activity. The processor then enters the low power state. When there is an interrupt caused by an external bus master, the processor is awaked from the low power state and the bus arbiter is re-enabled such that future bus transactions can occur.

REFERENCES:
patent: 5535400 (1996-07-01), Belmont
patent: 5630145 (1997-05-01), Chen
patent: 5652895 (1997-07-01), Poisner
patent: 5669003 (1997-09-01), Carmean et al.
patent: 5740454 (1998-04-01), Kelly et al.

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