Stochastic analysis process optimization for integrated...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

11301999

ABSTRACT:
An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces a large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance memos to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.

REFERENCES:
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patent: 2005/0235232 (2005-10-01), Papanikolaou et al.
Hatono et al.,“Modeling and Online Scheduling of Flexible Manufacturing Systems Using Stochastic Petri Nets” ,Feb. 1991, IEEE Transactions on Software Engineering, vol. 17, iss. 2, pp. 126-132.
Sethi et al.,“Hierarchical Production and Setup Scheduling in Stochastic Manufacturing Systems”, Dec. 1994, Proceedings of the 33rdIEEE Conference on Decision and Control, vol. 2, pp. 1571-1576.
Shi et al.,“Design and Optimization of Complex Real-Time Dependable Systems”, Feb. 1996, Proceedings of WORDS' 96., Second Workshop on Object-Oriented Real-Time Dependable Systems, pp. 218-224.
Soner et al.,“An Asymptotic Analysis of Hierarchical Control of Manufacturing Systems”, Dec. 1988, Proceddings of the 27thIEEE conference on Decision and Control, vol. 3, pp. 1856-1857.

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