Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2001-09-06
2003-06-10
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S088000, C326S092000
Reexamination Certificate
active
06577162
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a step-up circuit, and more particularly to a step-up circuit that uses MOS-FETs.
2. Conventional Technology
To write data in, for example, an E
2
PROM, a voltage of 12~18 V is required. However, power supply voltage in recent ICs is direct current voltage of 3~5 V, and therefore the power supply voltage must be stepped up by a step-up circuit in order to drive the E
2
PROM with such a voltage.
In general, in semiconductor integrated circuits including E
2
PROMs, the P-substrate process has been used in view of the device characteristic, and therefore step-up circuits that use N-channel MOS-FETs as substitution of diodes have been widely used.
FIG. 7
shows a circuit diagram of such a conventional step-up circuit described above.
Referring to
FIG. 7
, an oscillation block
1
includes a NAND circuit and an odd number of inversion circuits composed of inverters INV
41
, INV
42
, . . . which are circularly connected to one another, and capacitors C
41
, C
42
, . . . One terminal of each of the capacitors C
41
, C
42
, . . . is connected to an input terminal of each of the inverters INV
41
, INV
42
, . . . , respectively, and the other terminal is connected to a power supply voltage V
SS
on a low potential side (grounded in the example).
Also, a step-up block
2
includes rectification circuits in a plurality of stages. The rectification circuit in each of the stages includes one of the N-channel transistors (MOS-FETs) Q
51
, Q
52
, . . . , and one of the capacitors C
51
, C
52
, . . . A source of the transistor in each of the stages is connected to a drain and a gate of the transistor in the next stage. Furthermore, the transistor Q
55
that is connected to the rectification circuit in the last stage prevents reverse current from an output terminal.
Next, an operation of the step-up circuit is described. When a write control signal WR is input in the NAND gate, the oscillation block
1
starts an oscillation operation and outputs a clock signal. The clock signal output from the oscillation block
1
is inverted by an inverter INV
50
to become a clock signal CL
50
, which is further inverted by an inverter INV
51
to become an inverted clock signal CL
51
. The clock signal CL
50
and the inverted clock signal CL
51
are alternately supplied to the capacitors in the respective stages in the step-up block
2
, and rectified by the N-channel transistors in the respective stages. As a result, a direct current voltage that is stepped up from a power supply voltage V
DD
on a high potential side is generated on an output OUT of the step-up circuit.
It is noted that, among E
2
PROMs, in particular, those operating at a low voltage operate at a power supply voltage of 3V or lower. However, such E
2
PROMs still need a voltage of 15V or higher when a writing operation is performed. In this case, the step-up circuit described above does not provide enough stepped-up voltage, and therefore needs to be provided with an auxiliary step-up circuit at each of the stages in the step-up circuit.
FIG.
8
(
a
) shows a step-up cell
10
in which an auxiliary step-up circuit is connected to each of the stages of the step-up circuit. Also, FIG.
8
(
b
) shows in part a step-up circuit in which a plurality of the step-up cells
10
described above are connected to one another. Points A and B at which clock signals are input in each of the step-up cells
10
are alternately connected to two lines that carry clock signals &phgr;
1
and &phgr;
2
and to two lines that carry clock signals &phgr;
3
and &phgr;
4
. In this manner, by the step-up circuit shown in FIG.
8
(
b
), four-phase clocks having different phases are required. In order to make them, a timing generation circuit must be connected between the oscillation block and the step-up block. Accordingly, in the conventional art, a timing generation circuit shown in
FIG. 9
is used to generate four-phase clock signals shown in FIG.
10
.
Both of the oscillation block
1
and the step-up block
2
of the conventional step-up circuit shown in
FIG. 7
are equipped with capacitors. Therefore, when such a step-up circuit is integrated (into an IC), a problem occurs in that its chip area increases.
Also, a step-up circuit used in an E
2
PROM that operates at a low voltage, such as the one shown in FIG.
8
(
b
), needs to generate four-phase clock signals by a timing generation circuit. For this requirement, the chip area increases when it is integrated into an IC. Also, when the circuit is laid out on a substrate, a step-up block, an oscillation block and a timing generation block have to be disposed separately from one another, with the result that the placement effect deteriorates, which results in an increased chip area.
Furthermore, when step-up cells shown in FIG.
8
(
a
) are serially connected to obtain a required voltage, the first operation is normally performed. However, since a stepped-up charge of the previous round remains in the capacitors of the step-up circuit, an abnormality is generated in the waveform of stepped-up voltage. Also, since a charge-discharging period is required between a first step-up operation and a second step-up operation, a time loss occurs in writing in the memory.
In view of the above, it is a first object of the present invention to provide a step-up circuit that can reduce a chip area as compared to conventional techniques. Also, it is a second object of the present invention to provide a step-up circuit that has good area utilization efficiency. Furthermore, it is a third object of the present invention to provide a step-up circuit that minimizes abnormality generation in the step-up waveform and has a high step-up speed.
SUMMARY OF THE INVENTION
To solve the problems described above, a step-up circuit in accordance with one aspect of the present invention is a step-up circuit to step-up a direct current potential applied to a first node and output the same from a second node, comprising: a plurality of serially connected rectification elements between the first node and the second node; a plurality of capacitors connected to connection points of the plurality of rectification elements respectively; and an oscillation loop that is formed by circularly and serially connecting an odd number of inversion devices, each inverting an input signal and outputting the same, and supplying an alternating current signal having a specified phase to the plurality of capacitors.
Here, each of the plurality of capacitors may be formed from an N-channel transistor. Also, the plurality of capacitors may be connected between connection points of the plurality of rectification elements and connection points of the odd number of inversion devices, respectively. As a result, the capacitors can be commonly used by a step-up block and an oscillation block, so that the chip area can be reduced.
Also, a step-up circuit in accordance with a second aspect of the present invention is a step-up circuit to step-up a direct current potential applied to a first node and output the same from a second node, comprising: a first group of N-channel transistors with source and drain paths being serially connected between the first node and the second node; a second group of N-channel transistors that open and close paths between inputs and gates of the first group of N-channel transistors, respectively, according to a potential of an output of the first group of N-channel transistors; a first group of capacitors connected to connection points of the outputs of the first group of N-channel transistors, respectively; an oscillation loop that is formed by circularly and serially connecting an odd number of inversion devices, each inverting an input signal and outputting the same, and supplying an alternating current signal having a specified phase to the first group of capacitors; a second group of capacitors connected to gates of the first group of N-channel transistors, respectively; and a device that forms a signal to be supplied to the second group o
Harness & Dickey & Pierce P.L.C.
Seiko Epson Corporation
Tokar Michael
Tran Anh
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