Printing – Stenciling – Stencils
Reexamination Certificate
2002-05-20
2004-10-12
Evanisko, Leslie J. (Department: 2854)
Printing
Stenciling
Stencils
C101S114000, C118S213000
Reexamination Certificate
active
06802250
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the solder paste stencil printing process used in semiconductor wafer bumping, and more particularly to the stencils that are used in this process.
BACKGROUND OF THE INVENTION
Historically, most semiconductor dies were packaged using wire bonding. Wire bonding involves the attachment of thin gold or aluminum wires between die bonding pads and lead connections in the package. The resulting packaged semiconductor dies are then attached to printed circuit boards (PCB's), or otherwise utilized. Wire bonding presents several problems, however. There are resistances associated with each bond. There are minimum height limits imposed by the required wire loops. There is the chance of electrical performance problems or shorting if the wires come too close to each other.
These problems are addressed by flip-chip technology, which more recently has been supplanting wire bonding. Flip-chip joining is a chip or package connection process where bumps of connecting metal are formed on the chip surface, and the chip is flipped over for soldering to the package, PCB, or otherwise. The wires in wire bonding are thus replaced with a deposited metal bump on each bonding pad. Connection to the package or PCB is made when the chip is flipped over and soldered. Packages are lower profile and the electrical connection is of lower resistance. The electrical path is also much shorter.
One important part of flip-chip joining is the wafer bumping process. Wafer bumping is the placement or fabrication of the metal bumps on each bonding pad of a die. Such metal bumps, or balls, can be solder or another metal. Wafer bumping is performed when the semiconductor dies are still connected to one another in semiconductor wafer form. Typically, solder is deposited via stencil printing, and then reflowing is performed so that the deposited solder forms spherical balls, or bumps.
FIGS. 1A-1F
illustrate this solder-printing wafer-bumping process. In
FIG. 1A
, a semiconductor wafer
102
has a bonding pad
104
thereon, such as aluminum. A passivation layer
106
has been added on the wafer
102
such that only the bonding pad
104
is exposed. Because solder bumps do not adhere to aluminum pads, an under-bump metallization (UBM) layer
108
is sputtered. This is usually a trimetallic or bimetallic intermediary between the solder bumps and the aluminum pads. For instance, it may be a combination of aluminum, nickel vanadium, and copper.
In
FIG. 1B
, a photoresist mask
110
is added over the UBM layer
108
in the vicinity of the bonding pad
104
. The photoresist mask
110
is added in the conventional manner of applying photoresist, patterning the photoresist, and developing the photoresist. In
FIG. 1C
, the UBM layer
108
is etched away except for under the photoresist mask
110
. The photoresist mask
110
is then stripped or removed, as shown in
FIG. 1D
, leaving only the UBM layer
108
over the vicinity of the bonding pad
104
. Next, in
FIG. 1E
, solder paste
112
or another metal used for wafer bumping is stencil printed thickly over the UBM layer
108
. Finally, in
FIG. 1F
, the solder paste
112
is reflowed to form a solder bump.
The stencil printing process of
FIG. 1E
is more particularly shown in
FIG. 2
, which is a top view of a semiconductor wafer
204
within a stencil
202
. The stencil
202
is aligned over the semiconductor wafer
204
, where the stencil
202
has a pattern corresponding to the presence of aluminum pads and UBM layers thereover on the on the semiconductor wafer
204
. Once the stencil is aligned over the semiconductor wafer
204
, solder paste
208
is added to the top of the stencil
202
. A squeegee
210
is then used to apply the solder paste
208
over the stencil
202
, and onto the UBM layers and the aluminum pads of the wafer
204
as exposed through the stencil
202
. Generally, a number of passes, such as six, are made with the squeegee
210
over the wafer
204
.
FIG. 3
shows an enlarged side view of
FIG. 2
, where the edge of the semiconductor wafer
204
meets a typically designed stencil
202
′ according to the prior art. In particular, there is a gap
252
between the wafer
204
and the stencil
202
′, and the wafer
204
is substantially flush with the stencil
202
′ as to their top surfaces. Such an existing technology stencil for solder paste printing, however, can be problematic. As solder paste is squeegeed over the top surfaces of the stencil
202
′ and the wafer
204
, some solder paste may get into the gap
252
between the two, and potentially flow underneath the wafer
204
. This contamination is undesirable, and can increase the risk of the wafer
204
breaking, causing a decrease in yield.
Therefore, there is a need for preventing solder paste from flowing over the side of a semiconductor wafer and onto its backside during the solder paste stencil printing process. Such prevention should substantially eliminate solder paste contamination of the semiconductor wafer, and thus prevent yield reduction. For these and other reasons, therefore, there is a need for the present invention.
SUMMARY OF THE INVENTION
The invention relates to a stencil design for solder paste printing. A stencil for stencil printing of solder onto a semiconductor wafer for semiconductor wafer bumping includes a substrate. The substrate has a hole defined therein substantially shaped to correspond to and receptive to the semiconductor wafer. An interior edge of the substrate surrounds the hole, and has an upper lip under which the semiconductor wafer is positioned. The upper lip of the interior edge of the substrate surrounding the hole substantially prevents the solder from flowing onto sides and a bottom of the semiconductor wafer during stencil printing of the solder.
In one embodiment, the upper lip is rectangular in cross-profile shape. An outer interior edge of the substrate from the interior edge of the substrate having the upper lip is substantially adjacent to sides of the semiconductor wafer. The upper lip of the interior edge of the substrate surrounding the hole has an underside against which a top surface of the semiconductor wafer makes contact.
In another embodiment, the upper lip is triangular in cross-profile shape. An outer interior edge of the substrate from the interior edge of the substrate having the upper lip is such that a gap exists between the outer interior edge and sides of the semiconductor wafer. The upper lip of the interior edge of the substrate surrounding the hole has an angled-downward underside against which a top corner of the semiconductor wafer makes single-point contact.
Embodiments of the invention provide for advantages over the prior art. The top surface of the substrate is not flush with the top surface of the semiconductor wafer. During squeegeeing, the upper lip of the interior edge of the substrate prevents the solder from flowing onto the sides and the bottom of the semiconductor wafer. Where the upper lip has a rectangular cross-profile shape, this is because the adjacency of the underside of the upper lip to the top surface of the wafer prevents solder from flowing under underside of the upper lip, such that the solder does not reaches the sides or the bottom of the wafer. Where the upper lip has a triangular cross-profile shape, this is because the contact of a top corner of the semiconductor wafer with the angled underside of the upper lip prevents solder from flowing past this point of contact, such that solder does not reach the sides or the bottom of the wafer.
Still other advantages, aspects, and embodiments of the invention will become apparent by reading the detailed description that follows, and by referring to the accompanying drawings.
REFERENCES:
patent: 5460316 (1995-10-01), Hefele
patent: 5922496 (1999-07-01), Dalal et al.
patent: 6085968 (2000-07-01), Swindlehurst et al.
patent: 6631675 (2003-10-01), Brody et al.
patent: 61-249790 (1986-11-01), None
patent: 62-052554 (1987-03-01), None
patent: 02-112993 (1990-04-01), No
Chen Li-Chih
Chen Yen-Ming
Ching Kai-Ming
Lee Hsin-Hui
Lin Chia-Fu
Evanisko Leslie J.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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