Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-03-07
2006-03-07
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S105000
Reexamination Certificate
active
07010643
ABSTRACT:
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device in one embodiment can comprise control circuitry to perform an initialization operation on the synchronous memory, and a status register having at least one data bit that can be programmed to indicate if the initialization is being performed. A method of operating a memory system includes initiating an initialization operation on a memory device, and monitoring a memory status register to determine when the initialization operation is completed.
REFERENCES:
patent: 4684826 (1987-08-01), France et al.
patent: 5041886 (1991-08-01), Lee
patent: 5430852 (1995-07-01), Watanabe et al.
patent: 5515317 (1996-05-01), Wells et al.
patent: 5526364 (1996-06-01), Roohparvar
patent: 5537354 (1996-07-01), Mochizuki et al.
patent: 5600605 (1997-02-01), Schaefer
patent: 5615159 (1997-03-01), Roohparvar
patent: 5619461 (1997-04-01), Roohparvar
patent: 5666321 (1997-09-01), Schaefer
patent: 5675540 (1997-10-01), Roohparvar
patent: 5677885 (1997-10-01), Roohparvar
patent: 5734821 (1998-03-01), Chung et al.
patent: 5751039 (1998-05-01), Kauffman et al.
patent: 5787457 (1998-07-01), Miller et al.
patent: 5805927 (1998-09-01), Bowes et al.
patent: 5825782 (1998-10-01), Roohparvar
patent: 5835430 (1998-11-01), Henning et al.
patent: 5898621 (1999-04-01), Takahashi et al.
patent: 5933434 (1999-08-01), Roohparvar
patent: 5936903 (1999-08-01), Jeng et al.
patent: 5995438 (1999-11-01), Jeng et al.
patent: 6026465 (2000-02-01), Mills et al.
patent: 6028798 (2000-02-01), Roohparvar
patent: 6073204 (2000-06-01), Lakhani et al.
patent: 6084803 (2000-07-01), Sredanovic et al.
patent: 6137133 (2000-10-01), Kauffman et al.
patent: 6141247 (2000-10-01), Roohparvar et al.
patent: 6201739 (2001-03-01), Brown et al.
patent: 6275446 (2001-08-01), Abedifard
patent: 6292868 (2001-09-01), Norman
patent: 6378056 (2002-04-01), Nizar et al.
patent: 6456542 (2002-09-01), Roohparvar
Keeth, et al., “DRAM circuit design: a tutorial,” IEEE Press, 2001, pp. 16-23, 142-153.
Micron Semiconductor Products, Inc., “2Mb, Smart 5 BIOS-Optimized Boot Block Flash Memory,”Flash Memorywww.micron.com, copyright 2000, Micron Technology, Inc., pp. 1-12.
Micron, “16 Mb: x 16 SDRAM”Synchronous DRAM, www.micron.com, copyright 1999 Micron Technology, Inc., pp. 1-51.
Leffert Jay & Polglaze
Micro)n Technology, Inc.
Thai Tuan V.
LandOfFree
Status register to improve initialization of a synchronous... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Status register to improve initialization of a synchronous..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Status register to improve initialization of a synchronous... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3593534