Communications: electrical – Digital comparator systems
Patent
1987-03-17
1989-01-10
Harkcom, Gary V.
Communications: electrical
Digital comparator systems
3647365, G05B 100, G06F 702, G06F 738
Patent
active
047976527
ABSTRACT:
A unique circuit that unambiguously provides an output status bit and an output delta bit in response to an input data signal. This circuit does not require the use of a one shot. The circuit includes a first latch which latches the last status value, and an exclusive OR gate for comparing the previous input data value with the present input data value and provides an output data signal indicating whether change in the input data has occurred. If the exclusive OR gate indicates that a change in input data has occurred since the previous read, the new value of the input data is provided as an output status signal. Conversely, if the exclusive OR gate indicates that a change in the input signal has not occurred, the previous value of the input signal stored by the circuit is provided as an output status signal. Additional latches, which close at the onset of a read cycle, prevent either the delta bit or the status bit from changing during the read cycle. Another latch is set by the output status signal from the exclusive OR gate when the input data changes, and is only cleared by an actual read of delta bit which indicates that a change in input data has occurred, so a change in input data cannot be missed. A reset line initializes the circuit by clearing the latches and latching the present input data value into the location where the previously read input data value was stored.
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Aaker Mark
Harkcom Gary V.
National Semiconductor Corporation
Patch Lee
Shaw Dale M.
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