Status register architecture for flexible read-while-write...

Details Status register architecture for flexible read-while-write... Status register architecture for flexible read-while-write...

2005-08-16

2005-08-16

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S005000, C711S103000, C711S156000, C711S168000, C711S169000, C711S173000

Reexamination Certificate

active

06931498

ABSTRACT:
A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based on two partitions. A microcontroller is used to traffic the status register to memory array communication.

REFERENCES:
patent: 5765017 (1998-06-01), Hoy et al.
patent: 5867430 (1999-02-01), Chen et al.
patent: 5954828 (1999-09-01), Lin
patent: 5995415 (1999-11-01), Kuo et al.
patent: 6088264 (2000-07-01), Hazen et al.
patent: 6182189 (2001-01-01), Alexis et al.
patent: 6260103 (2001-07-01), Alexis et al.
patent: 2001/0011318 (2001-08-01), Dalvi et al.
patent: 2002/0095545 (2002-07-01), Dalvi et al.

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