Status holding circuit and status holding method

Details Status holding circuit and status holding method Status holding circuit and status holding method

2011-03-15

2011-03-15

Tan, Vibol (Department: 2819)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S144000, C714S048000, C714S054000

Reexamination Certificate

active

07908444

ABSTRACT:
A status holding circuit includes status holding sections of M stages (M is an integer equal to or more than 2) connected in series. Each of the status holding sections includes: N latches (N is an integer equal to or more than 2) provided for N input signals to N input terminals, respectively; and a switch circuit configured to set a data to a jthlatch of the N latches in an ithstatus holding section of the M-stage status holding sections when a status signal is supplied to a jthinput terminal of the N input terminals at an ithtiming.

REFERENCES:
patent: 4853929 (1989-08-01), Azuma et al.
patent: 5034744 (1991-07-01), Obinata
patent: 5426682 (1995-06-01), Takatsu
patent: 5724537 (1998-03-01), Jones
patent: 6035126 (2000-03-01), Wise et al.
patent: 6067417 (2000-05-01), Wise et al.
patent: 6209069 (2001-03-01), Baltar
patent: 6233680 (2001-05-01), Bossen et al.
patent: 6446179 (2002-09-01), Baltar
patent: 63-73435 (1988-04-01), None

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