Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2007-09-11
2007-09-11
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S149000, C711S151000, C710S052000, C710S057000, C365S189050
Reexamination Certificate
active
11040893
ABSTRACT:
A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M−(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.
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patent: 2006/0017497 (2006-01-01), Mo et al.
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Au Mario
Mo Jason Z.
Wu Cheng-Han
Bever Hoffman & Harms LLP
Bragdon Reginald
Cardwell Eric
Integrated Device Technology Inc.
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