Static type semiconductor memory device that can suppress...

Details Static type semiconductor memory device that can suppress... Static type semiconductor memory device that can suppress...

2000-06-29

2001-12-25

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S154000, C365S225700, C365S226000

Reexamination Certificate

active

06333877

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to static type semiconductor memory devices, and particularly to a static type semiconductor memory device with a spare column or spare row for replacing a defective memory cell row or defective memory cell column.
2. Description of the Background Art
FIG. 39
is a circuit diagram showing a structure of a memory cell of a static type random access memory (referred to as SRAM hereinafter) formed of conventional MOS transistors.
Referring to
FIG. 39
, a conventional memory cell includes a P channel MOS load transistor P
11
and an N channel MOS driver transistor N
11
connected in series between a power supply potential Vcc and a ground potential GND, and a P channel MOS load transistor P
12
and an N channel MOS driver transistor N
12
connected in series between power supply potential Vcc and ground potential GND. The connection node of P channel MOS load transistor P
11
and N channel MOS driver transistor N
11
is referred to as a storage node nm
1
. The connection node between P channel MOS load transistor P
12
and N channel MOS driver transistor N
12
is referred to as a storage node nm
2
.
Transistors P
11
and N
11
have their gates connected to storage node nm
2
. Transistors P
12
and N
12
have their gates connected to storage node nm
1
.
The conventional memory cell further includes an N channel MOS access transistor Tra
1
provided between a bit line BL and storage node nm
1
, and having a gate potential controlled by a word line WL, and an N channel MOS access transistor Tra
2
provided between storage node nm
2
and a bit line/BL, and having a gate potential controlled by word line WL.
FIG. 40
is a diagram showing a concept of short-circuit between storage nodes of SRAM memory cells. As shown in
FIG. 40
, there is a case where short-circuit occurs between two storage nodes in an SRAM caused by foreign objects in the wiring or contact formation processes or by defocus in photolithography.
Such a chip that has bit error is generally subjected to a replacement process with a redundant column or row in order to be shipped as an acceptable product.
Even if this chip is passed as a product acceptable from the standpoint of memory operation by the redundancy replacement, short-circuit of the storage nodes in the case of a full CMOS SRAM cell implies that there is still a path through which a current flows from power supply potential Vcc to ground potential GND as shown in FIG.
40
.
The existence of a current path in a defective memory cell becomes the cause of standby current defect in an SRAM of low power consumption. There was a problem that such a chip could not be shipped eventually as an acceptable product even if redundancy replacement is carried out.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a static type semiconductor memory device of favorable yield and having a standby current that becomes lower than the specification value.
According to an aspect of the present invention, a static type semiconductor memory device includes a regular memory cell array, a redundant memory cell array, a first power supply node, a plurality of first lines, and a potential supply control circuit.
The regular memory cell array has a plurality of memory cells arranged in a matrix. Each memory cell can retain a first level and a second level. The regular memory cell array is divided into a plurality of units of memory cell replacement.
The redundant memory cell array carries out redundancy repair for every memory cell replacement unit in the regular memory cell array.
The first power supply node is supplied with a first potential corresponding to the first level.
The plurality of first lines are provided corresponding to every memory cell replacement unit to supply the first potential from the power supply node to a memory cell in a corresponding memory cell replacement unit.
The potential supply control circuit can stop independently the supply of the first potential from the power supply node to the plurality of first lines.
According to another aspect of the present invention, a static type semiconductor memory device includes a regular memory cell array, a redundant memory cell array, a plurality of first lines, and a plurality of potential retain circuits.
The regular memory cell array has a plurality of memory cells arranged in a matrix. Each memory cell can retain a first level and a second level. The regular memory cell array is divided into a plurality of units of memory cell replacement.
The redundant memory cell array carries out redundancy repair for every unit of memory cell replacement in the regular memory cell array.
The plurality of first lines are provided corresponding to every memory cell replacement unit to supply the first potential from the power supply node to a memory cell in a corresponding memory cell replacement unit in a normal operation.
The plurality of potential retain circuits are provided corresponding to the plurality of first lines, respectively, to precharge the potential of a corresponding first line to a second potential corresponding to the second level after initiation of power supply to the static type semiconductor memory device, and supplying the first potential to a corresponding first line in response to a corresponding memory cell placement unit being accessed.
A main advantage of the present invention is that leakage current in a standby status can be suppressed since supply of the first potential to the first line is stopped when redundancy replacement is performed.
Another advantage of the present invention is that leakage current can be suppressed in a standby status since supply of the first potential to the first line is stopped in the memory cell placement unit that is to be subjected to redundancy replacement.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5579266 (1996-11-01), Tahara
patent: 5687178 (1997-11-01), Herr
patent: 5706231 (1998-01-01), Kokubo
patent: 6018488 (2000-01-01), Mishima et al.
patent: 3-212899 (1991-09-01), None
patent: 5-314790 (1992-05-01), None

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