Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2000-04-10
2001-10-23
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S156000, C365S227000
Reexamination Certificate
active
06307772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to static type semiconductor memory devices, and more particularly to a static type semiconductor memory device which includes a spare column to replace a defective column.
2. Description of the Background Art
In an SRAM which has a bit line and a line of a ground potential GND that are formed of the same interconnection layer, an extraneous object or defocusing brought about by the process of interconnection formation may short-circuit the bit line and the ground potential GND line. Since the bit line which is short-circuited with the ground potential GND line is fixed to a low level, a defective column which includes such a bit line cannot perform correct writing and reading operations.
Conventional SRAMs have been improved in the yield of chips by replacing such defective columns with normal spare columns.
However, even if such a defective column is replaced by a spare column, the conventional SRAM continues to flow current from a line of a power supply potential VCC through a bit line load and a defective bit line to a line of a ground potential GND, and increases current consumption.
Especially, recent lower power consumption type SRAMs excessively increase standby current even if a defective column as described above is replaced by a spare column, and thus the SRAMs become defective.
SUMMARY OF THE INVENTION
Therefore, a major object of the present invention is to provide a static type semiconductor memory device which consumes less current.
Briefly, a breaking circuit is provided which is arranged to correspond to each bit line pair and, in response to a corresponding bit line assuming a reference potential between first and second power supply potentials, breaks current flowing from a line of the first power supply potential through a corresponding bit line load to the bit line that has assumed the reference potential. Therefore, even if the bit line and a line of the second power supply potential are short-circuited, current leakage from the first power supply potential line through the bit line load and the bit line to the second power supply potential line can be prevented, and current consumption can be reduced.
Preferably, the breaking circuit includes a switching element provided to correspond to each bit line and connected in series with the bit line load between the line of the first power potential and one end of a corresponding bit line, and a potential detecting circuit provided to correspond to each bit line and rendering a corresponding switching element non-conductive in response to a corresponding bit line assuming a potential between the reference potential and the second power supply potential. In this case, only a bit line of the bit line pair which has assumed the potential between the reference potential and the second power supply potential is disconnected from the first power supply potential line.
Preferably, the switching element is a first transistor of a first conductivity type, and the potential detecting circuit includes an inverter having a second transistor of the first conductivity type and a third transistor of a second conductivity type which are connected in series between the lines of the first and second power supply potentials. In this case, the second and first transistors are rendered conductive and non-conductive, respectively, in response to the bit line assuming the potential between the reference potential and the second power supply potential.
Preferably, at least one diode element is further provided which is inserted between the line of the first power supply potential and a first electrode of the second transistor or between a first electrode of the third transistor and the second power supply potential line. In this case, the second and third transistors of the inverter are rendered conductive simultaneously, and through current can be prevented from flowing.
Preferably, the bit line load is a diode element having one electrode connected to the line of the first power supply potential and the other electrode connected to one end of a corresponding bit line through the first transistor, and the first electrode of the second transistor is connected to the other electrode of the diode element. In this case, the diode element which forms the bit line load also serves as a diode element for preventing through current, thus reducing the layout area.
Preferably, the breaking circuit includes a switching element provided to correspond to each bit line and connected in series with the bit line load between the line of the first power supply potential and one end of a corresponding bit line, and a potential detecting circuit to render a corresponding switching element non-conductive in response to at least one bit line of a corresponding bit line pair assuming a potential between the reference potential and the second power supply potential. In this case, the bit line pair is disconnected from the first power supply potential in response to at least one bit line of the bit line pair assuming the potential between the reference potential and the second power supply potential.
Preferably, the switching element is a first transistor of a first conductivity type, and the potential detecting circuit includes an NAND gate having second and third transistors of the first conductivity type connected in parallel between the line of the first power supply potential and an input electrode of the first transistor, and fourth and fifth transistors connected in series between a line of the second power supply potential and the input electrode of the first transistor. In this case, at least one of the second and third transistors is rendered conductive and the first transistor is rendered non-conductive in response to at least one bit line of the bit line pair assuming the potential between the reference potential and the second power supply potential.
Preferably, at least one diode element is further provided which is inserted between the line of the first power supply potential and first electrodes of the second and third transistors or between a first electrode of the fourth transistor and the line of the second power supply potential. In this case, the second to fifth transistors of the NAND gate are rendered conductive simultaneously, thus preventing the flow of through current.
Preferably, the bit line load is a diode element having one electrode connected to the line of the first power supply potential and the other electrode connected to one end of a corresponding bit line through the first transistor, and the first electrodes of the second and third transistors are connected to the other electrodes of the corresponding one and the other diode elements, respectively. In this case, the diode element which forms the bit line load also serves as a diode element for preventing through current, thus reducing the layout area.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4578778 (1986-03-01), Aoyama
patent: 4751683 (1988-06-01), Wada et al.
patent: 5706231 (1998-01-01), Kokubo
patent: 58-41486 (1983-03-01), None
patent: 6-195997 (1994-07-01), None
Ho Hoai V.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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