Static type semiconductor memory device adopting a...

Details Static type semiconductor memory device adopting a... Static type semiconductor memory device adopting a...

2001-05-02

2002-04-16

Zarabian, A. (Department: 2829)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S156000, C365S225700

Reexamination Certificate

active

06373760

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static type semiconductor memory device, and more particularly to a static type semiconductor memory device adopting a redundancy system for replacing a defective row or column with a spare row or column.
2. Description of the Background Art
FIG. 10
is a circuit block diagram illustrating a construction of a conventional static random access memory (hereafter referred to as SRAM).
Referring to
FIG. 10
, this SRAM includes a plurality of memory cells MC arranged in plural rows and plural columns (four rows and four columns in the example shown in FIG.
10
), a word line WL provided corresponding to each row, and a pair of bit lines BL, /BL provided corresponding to each column.
This SRAM further includes bit line loads
31
,
32
provided corresponding to each pair of bit lines BL, /BL for charging the corresponding pair of bit lines BL, /BL to an “H” level, a pair of data input/output lines IO, /IO, a column selection gate
33
provided corresponding to each pair of bit lines BL, /BL for connecting between the corresponding pair of bit lines BL, /BL and the pair of data input/output lines IO, /IO, and a column selection line CSL provided corresponding to each pair of bit lines BL, /BL.
The bit line loads
31
,
32
include a pair of P-channel MOS transistors that are respectively connected between the power source potential VDD and one end of the bit lines BL, /BL, and whose gates are both connected to the line of a ground potential VSS. The column selection gate
33
includes a pair of N-channel MOS transistors that are respectively connected between the other end of the bit lines BL, /BL and one end of the data input/output lines IO, /IO and whose gates are both connected to a column decoder
37
via the column selection line CSL.
Further, this SRAM includes a row decoder
34
, a control circuit
36
, a column decoder
37
, a writing circuit
38
, and a reading circuit
39
. The row decoder
34
selects one word line WL from a plurality of word lines WL in accordance with a row address signal given from the outside, and raises the selected word line WL from an “L” level, i.e. a non-selected level, to an “H” level, i.e. a selected level. The row decoder
34
includes an N-channel MOS transistor
35
provided corresponding to each word line WL for setting the corresponding word line WL to be at an “L” level, i.e. the non-selected level.
FIG. 10
shows a state in which the power source potential VDD is given to the gate of each N-channel MOS transistor
35
, and each word line WL is grounded via the corresponding N-channel MOS transistor
35
. The control circuit
36
controls the entire SRAM in accordance with a control signal given from the outside. The column decoder
37
selects one column selection line CSL from a plurality of column selection lines CSL in accordance with a column address signal given from the outside, and raises the selected column selection line CSL from the “L” level, i.e. the non-selected level, to the “H” level, i.e. the selected level.
The writing circuit
38
and the reading circuit
39
are both connected to the other end of the pair of data input/output lines IO, /IO. The writing circuit
38
writes data DI given from the outside into a memory cell MC selected by the row decoder
34
and the column decoder
37
. The reading circuit
39
outputs read data DO from a memory cell MC selected by the row decoder
34
and the column decoder
37
to the outside.
Next, an operation of the SRAM shown in
FIG. 10
will be described. At the time of a writing operation, the word line WL of the row corresponding to the row address signal is raised to the “H” level, i.e. the selected level, by the row decoder
34
, and each memory cell MC in the row is activated. Subsequently, the column selection line CSL of the column corresponding to the column address signal is raised to the “H” level, i.e. the selected level, by the column decoder
37
, and the activated memory cell MC in the column is connected to the writing circuit
38
via the pair of bit lines BL, /BL, the column selection gate
33
, and the pair of data input/output lines IO, /IO.
The writing circuit
38
sets one of the pair of data input/output lines IO, /IO to be at the “H” level and sets the other to be at the “L” level in accordance with the data DI given from the outside, so as to write data DI into an activated memory cell MC. When the word line WL and the column selection line CSL are lowered to the “L” level, i.e. the non-selected level, the data are stored into the memory cell MC.
In a reading operation, the column selection line CSL of the column corresponding to the column address signal is raised to the “H” level, i.e. the selected level, by the column decoder
37
, and each memory cell MC in the selected column is connected to the reading circuit
39
via the pair of bit lines BL, /BL, the column selection gate
33
, and the pair of data input/output lines IO, /IO. Subsequently, the word line WL of the row corresponding to the row address signal is raised to the “H” level, i.e. the selected level, by the row decoder
34
, so as to activate each memory cell MC in the row. This allows electric currents to flow from one of the pair of bit lines BL, /BL to the memory cell MC in accordance with the data stored in the memory cell MC selected by the decoders
37
,
34
, whereby the potential of one of the pair of data input/output lines IO, /IO goes down. The reading circuit
39
compares the potentials of the data input/output lines IO, /IO, and outputs data DO to the outside in accordance with the comparison results.
FIG. 11A
is a circuit diagram illustrating a construction of a memory cell MC. Referring to
FIG. 11A
, the memory cell MC includes load transistors (P-channel MOS transistors)
41
,
42
, driver transistors (N-channel MOS transistors)
43
,
44
, and access transistors (N-channel MOS transistors)
45
,
46
. The P-channel MOS transistors
41
,
42
are respectively connected between the memory cell power source line MVL and storage nodes N
1
, N
2
, and the gates of the P-channel MOS transistors
41
,
42
are respectively connected to the nodes N
2
, N
1
. The power source potential VDD is supplied to the memory cell power source line MVL. The N-channel MOS transistors
43
,
44
are respectively connected between the storage nodes N
1
, N
2
and a memory cell ground line MGL, and the gates of the N-channel MOS transistors
43
,
44
are respectively connected to the nodes N
2
, N
1
. The N-channel MOS transistors
45
,
46
are respectively connected between the storage nodes N
1
, N
2
, and the bit lines BL, /BL, and the gates of the N-channel MOS transistors
45
,
46
are both connected to the word line WL.
In a writing operation, one of the bit lines BL, /BL is set to be at the “H” level and the other is set to be at the “L” level in accordance with the writing data DI. Subsequently, the word line WL is set to be at the “H” level, i.e. the selected level, whereby the N-channel MOS transistors
45
,
46
become electrically conducted, and the levels of the bit lines BL, /BL are respectively given to the storage nodes N
1
, N
2
. When the “H” level and the “L” level are respectively given to the storage nodes N
1
, N
2
, the MOS transistors
41
,
44
become electrically conducted, and the MOS transistors
42
,
43
become electrically non-conducted, whereby the levels of the storage nodes N
1
, N
2
are latched by the MOS transistors
41
to
44
. Further, when the “L” level and the “H” level are respectively given to the storage nodes N
1
, N
2
, the MOS transistors
42
,
43
become electrically conducted, and the MOS transistors
41
,
44
become electrically non-conducted, whereby the levels of the storage nodes N
1
, N
2
are latched by the MOS transistors
41
to
44
. When the word line WL is set to be at the “L” level, i.e. the non-selected level, the N-channel MOS transistors
45
,
46
become electrically non-conducted, whereby the levels of the storage nodes N
1
, N
2
a

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