Static-type semiconductor memory device

Details Static-type semiconductor memory device Static-type semiconductor memory device

2002-03-14

2003-06-10

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257S904000, C365S051000, C365S154000

Reexamination Certificate

active

06577021

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static-type semiconductor memory device (hereinafter referred to as SRAM (Static Random Access Memory)), in particular, to a memory cell structure of an SRAM.
2. Description of the Background Art
FIGS. 13
to
16
show a layout of memory cells of a conventional SRAM. In these figures two memory cells
1
and a well contact cell
2
are shown. In the case that a well contact region is formed in, respectively, all of the memory cells
1
, the area of the memory cell
1
increases and, therefore, a well contact cell
2
is formed for a plurality of memory cells
1
so as to achieve the reduction of the area of the memory cell array.
As shown in
FIG. 13
, memory cells
1
are arranged, respectively, above and below well contact cell
2
. Memory cells
1
and well contact cell
2
both have an n well in the middle and have p wells on both the right and left sides of this n well.
One memory cell
1
has six MOS Metal Oxide Semiconductor) transistors. In more detail, memory cell
1
has n type access MOS transistors Q
1
, Q
2
, n type driver MOS transistors Q
3
, Q
4
as well as p type load MOS transistors Q
5
and Q
6
.
In upper memory cell
1
, access MOS transistor Q
1
is formed at a part where a diffusion region
40
i
and a polysilicon layer
3
b
cross, access MOS transistor Q
2
is formed at a part where a diffusion region
40
a
and a polysilicon layer
3
c
cross, driver MOS transistor Q
3
is formed at a part where diffusion region
40
i
and a polysilicon layer
3
d
cross, driver MOS transistor Q
4
is formed at a part where diffusion region
40
a
and a polysilicon layer
3
a
cross, load MOS transistor Q
5
is formed at a part a diffusion region
40
d
and polysilicon layer
3
a
cross and load MOS transistor Q
6
is formed at a part where a diffusion region
40
e
and polysilicon layer
3
d
cross.
In lower memory cell
1
, access MOS transistor Q
1
is formed at a part where a diffusion region
40
k
and a polysilicon layer
3
j
cross, access MOS transistor Q
2
is formed at a part where a diffusion region
40
c
and a polysilicon layer
3
k
cross, driver MOS transistor Q
3
is formed at a part where diffusion region
40
k
and a polysilicon layer
3
l
cross, driver MOS transistor Q
4
is formed at a part where diffusion region
40
c
and a polysilicon layer
3
i
cross, load MOS transistor Q
5
is formed at a part where a diffusion region
40
g
and polysilicon layer
3
i
cross and load MOS transistor Q
6
is formed at a part where a diffusion region
40
h
and polysilicon layer
3
l
cross.
Well contact cell
2
has diffusion regions
40
b
,
40
f
,
40
j
and polysilicon layers
3
e
,
3
f
,
3
g
and
3
h.
FIG. 14
shows a layout of contact parts
5
,
5
e
to
5
f
and
5
i
. As shown in
FIG. 14
, predetermined regions in diffusion regions
40
a
to
40
k
are electrically connected to upper layer wires via contact part
5
,
5
e
to
5
f
and
5
i
. In addition, a predetermined polysilicon layer from among polysilicon layers
3
a
to
3
l
is also electrically connected to an upper layer wire, or the like, via contact part
5
.
P
+
diffusion regions
40
b
and
40
j
are fixed at the ground potential via contact parts
5
e
and
5
f
and, thereby, the p well is fixed at the ground potential. In addition, n
+
diffusion region
40
f
is fixed at the power supply potential via contact part
5
i
and, thereby, the n well is fixed at the power supply potential.
Polysilicon layers
3
e
and
3
f
are dummy layers for securing the periodicity of polysilicon layers of upper memory cell
1
in FIG.
13
. In addition, polysilicon layers
3
g
and
3
h
are dummy layers for securing the periodicity of polysilicon layers of lower memory cell
1
in FIG.
13
.
FIG. 15
shows first metal wire layers
7
, with first via holes
6
, formed in a layer above polysilicon layers
3
a
to
3
l.
As shown in
FIG. 15
, first metal wire layers
7
are formed so as to make connections between contact parts
5
or between contact parts
5
and contact parts
5
e
,
5
f
and
5
i
while first via holes
6
are created at predetermined positions in first metal wire layers
7
.
FIG. 16
shows a layout of second metal wire layers
9
and third metal wire layers
10
a
to
10
e
, with second via holes
8
, formed in a layer above first metal wire layers
7
.
As shown in
FIG. 16
, first metal wire layers
7
and second metal wire layers
9
are connected via first via holes
6
while second metal wire layers
9
and third metal wire layers
10
a
to
10
e
are connected via second via holes
8
.
In the above conventional SRAM, as shown in
FIG. 13
, insulation regions are formed between diffusion regions
40
b
,
40
f
,
40
j
within well contact cell
2
and diffusion regions
40
a
,
40
c
,
40
e
,
40
g
,
40
i
,
40
k
within memory cell
1
so as to separate these regions. Therefore, the length L of well contact cell
2
in the upper and lower direction of
FIG. 13
becomes larger than the length L
1
of memory cell
1
so that the areas of memory cell
1
and well contact cell
2
become different.
In addition, by separating diffusion regions in well contact cell
2
as described above, the regularity of the pattern (in particular, diffusion region pattern or polysilicon layer pattern) which is repeated regularly among adjoining memory cells
1
is disturbed in well contact cell
2
. That is to say, the existence of well contact cell
2
disturbs the periodicity of the pattern layout.
Diffusion regions
40
a
to
40
k
and polysilicon layers
3
a
to
3
l
are usually formed by using a photolithographic technology and in the case that the periodicity of the pattern layout is disturbed as described above, a dispersion of the size of the pattern is easily caused at the time of the formation of each pattern. Therefore, a problem arises that the dispersion of the transistor characteristics is easily caused.
Here, as shown in
FIG. 13
, by arranging polysilicon layers
3
e
,
3
f
,
3
g
and
3
h
as dummy layers, the fluctuation of the periodicity of the polysilicon layers in memory cells
1
can be restricted to a certain degree. However, this effect becomes smaller together with the miniaturization of memory cells
1
and the effect is not very apparent for the miniaturized memory cells
1
.
In addition, as for a layout wherein the periodicity of the pattern of memory cells
1
is taken into consideration, the layout shown in U.S. Pat. No. 6,128,208 can be cited. According to the invention described in this reference, however, well contact cell
2
is not provided and the idea of the layout in the case that well contact cell
2
is provided is not disclosed in this reference.
SUMMARY OF THE INVENTION
The present invention is provided in order to solve the above problem. A purpose of the present invention is to prevent the periodicity of the pattern layout of diffusion regions, polysilicon layers, or the like, from being disturbed in an SRAM which has well contact cells and memory cells.
An SRAM (static-type semiconductor memory device) according to the present invention comprises a plurality of memory cells and well contact cells. The memory cells do not have a well contact region and provided over a plurality of wells for storing data. The well contact cells for fixing the potential of the wells are provided over a plurality of wells so as to adjoin memory cells. The area of a memory cell and the area of a well contact cell are equal.
By making the area of a memory cell and the area of a well contact cell equal, as described above, a pattern similar to that within a memory cell, such as for diffusion regions or for polysilicon layers (gates), can be formed in the same manner in a well contact cell. Thereby, the periodicity of the above pattern can be prevented from being disturbed in well contact cells.
A memory cell has a first diffusion region of a first conductive type while a well contact cell has a second diffusion region of a second conductive type for fixing the potential

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