Static information storage and retrieval – Read/write circuit – For complementary information
Patent
1992-08-13
1994-04-19
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
For complementary information
36518911, 365202, 365203, 365154, 365205, G11C 700
Patent
active
053052641
ABSTRACT:
A static type random access memory device supplies current from a load circuit to a selected digit line pair in a write-in phase of operation, and the load circuit comprises a first pair of charging transistors coupled between a positive power voltage line and the selected digit line pair in a read-out phase, and a second pair of charging transistor also coupled between the positive power voltage line and the selected digit line pair and responsive to differential voltage indicative of a write-in data bit for selectively coupling one of the digit lines with the positive power voltage line so that the impedance of the load circuit is appropriately adjustable between the read-out phase and the write-in phase.
REFERENCES:
patent: 4760561 (1988-07-01), Yamamoto et al.
patent: 4933905 (1990-06-01), Ootani
patent: 5034924 (1991-07-01), Taniguchi et al.
patent: 5157631 (1992-10-01), Shimogawa
Odaka, M., et al, A 512 KB/5 ns BiCMOS RAM with 1 KG/150 ps Logic Gate Array, Feb. 15, 1989, 1989 IEEE International Solid-State Circuits Conference.
LaRoche Eugene R.
Mai Son
NEC Corporation
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