Static type memory cell structure with parasitic capacitor

Details Static type memory cell structure with parasitic capacitor Static type memory cell structure with parasitic capacitor

1996-03-29

1999-06-29

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

257904, 257532, 257534, H01L 2711

Patent

active

059172479

ABSTRACT:
The semiconductor memory device disclosed includes an element isolation insulating film, a first diffusion layer, a second diffusion layer. The first diffusion layer of a first conductivity type is buried inside the semiconductor substrate, and has an impurity concentration higher than that of the semiconductor substrate. The first diffusion layer is provided at a shallow position in the area where the element isolation insulating film is formed and is provided a deep position in the area where the element isolation insulating film is not formed. The second diffusion layer of a second conductivity type is at an area ranging from the surface of the semiconductor substrate to the first diffusion layer inside the semiconductor substrate. A p-n junction is formed at a junction portion between the first and second diffusion layers. The structure thus configured has a high resistance to soft errors.

REFERENCES:
patent: 4894696 (1990-01-01), Takeda et al.
patent: 5548149 (1996-08-01), Joyner
patent: 5691564 (1997-11-01), Oyamatsu

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