Electronic digital logic circuitry – Three or more active levels
Reexamination Certificate
2002-07-01
2004-03-30
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Three or more active levels
C326S016000, C326S093000, C326S105000, C326S098000, C714S724000, C714S725000
Reexamination Certificate
active
06714045
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to power management in dynamic logic. More specifically, the present invention relates to the use of static signals within a dynamic logic design to transmit data across a distance to reduce the overall power consumption of the logic design.
2. Description of the Related Art
High performance complementary metal-oxide semiconductor (CMOS) very large scale integrated (VLSI) circuits are increasingly using dynamic logic gates to improve circuit performance. Dynamic logic gates are fast but require a frequent refresh to hold a logic state. Constantly switching transistors on and off to precharge and then evaluate dynamic logic gates consumes an enormous amount of power. Accordingly, because of the power and noise constraints on dynamic logic gates, many high-performance CMOS VLSI are designed using conventional static logic gates outside the critical path of the logic. Static circuits hold state without a frequent refresh. Since power is consumed only when the inputs switch, static circuits consume much less power than dynamic circuits.
However, static circuits are generally slower than dynamic circuits, and mixing the two has been problematic. Static flip-flops have been used to interface dynamic logic and static logic, but this typically creates timing and performance problems due to the long setup and hold times associated with static flip-flops.
Static signals which feed dynamic gates must be stable by the time the dynamic gate goes into its evaluate state for every cycle, since dynamic gates require monotonic inputs. Once an N-tree has been discharged, it cannot be pulled high again until the next pre-charge phase. This means that a static input signal to a dynamic gate cannot transition from high-to-low during the evaluate phase of the gate if the static input signal's high value has been allowed to start switching the gate. Designers have thus typically imposed long setup time requirements on static signals that are inputs to dynamic logic to insure that a static input signal has arrived and is stable and not oscillating before the gate evaluates. In the past, designers have accommodated the setup requirement by simply operating the design at a slower clock rate, thus giving the static flip-flop adequate time to provide stable output signals to the dynamic logic gate before the dynamic logic gate enters the evaluation period. Alternatively, some designers have inserted a clock delay between a static flip-flop and the dynamic gate the flip-flop is driving, to delay the gate's evaluation phase enough to insure that the flip-flop's outputs are stable. Neither solution is practical for today's high performance circuits. The timing constraints that typical static flip-flops impose on designers trying to use them in dynamic logic is described in detail in the U.S. Pat. No. 6,118,304 (hereinafter, the “Logic Synchronization Patent”), which is incorporated by reference for all purposes into this specification.
The Logic Synchronization Patent, and the documents referenced therein (specifically, U.S. patent application Ser. No. 09/019,355, now U.S. Pat. No. 6,066,965, entitled “Method and Apparatus for a Logic Circuit using 1 of 4 Signals” (hereinafter, “the NDL patent”)) also describe the use of NDL or N-NARY dynamic logic and a novel multiphase clock scheme for logic timing and synchronization that makes extensive use of ‘time-borrowing’ to achieve the extremely fast logic required for current high-performance applications. N-NARY logic, also known as FAST14 logic, is a new logic family developed by Intrinsity Inc. (f/k/a EVSX Inc.), the Assignee of this application. Although, as the NDL patent details, the FAST14 logic technology includes features that cause circuits implemented in FAST14 logic (denoted as “NDL gates” or “NDL designs”) to consume much less power than traditional dual-rail dynamic logic, even highly complex NDL designs can suffer some of the power problems associated with the high switch factor of traditional dynamic logic. Consequently, designers of NDL circuits and systems may find it advantageous to utilize design approaches and methods typically found in static logic to reduce the system's power consumption. For example, U.S. patent application Ser. No. 10/187,879, filed on Jul. 2, 2002, and entitled “Static Storage Element for Dynamic Logic” (hereinafter, “the Static Storage Element Patent”) describes two different embodiments of a static storage element suitable for use in NDL designs. As described in the Static Storage Element patent, these storage devices statically store the output of dynamic logic gates for a user-specified number of clock cycles, and then provide the output to downstream dynamic logic gates. Designers using FAST14 technology can use the static storage devices in lieu of dynamic buffers, thereby eliminating the power consumed by the buffers' constantly switching transistors. The NDL Patent and the Static Storage Element patent are incorporated by reference for all purposes into this specification. Additionally, FAST14 logic and some common structures, features, and functions of FAST14 logic are further described in U.S. Pat. No. 6,069,497, (FAST14 Circuit Using 1 of N Signals), U.S. Pat. No. 6,219,686 (Sum/HPG Adder/Subtractor Gate), U.S. Pat. No. 6,202,194 (Twizzle), U.S. Pat. No. 6,324,239 (Shifter), and U.S. Pat. No. 6,269,387 (3-Stage 32-Bit Adder), all of which are incorporated by reference for all purposes into this specification.
As described in the NDL patent and the Logic Synchronization Patent, the various speed advantages that the FAST14 dynamic logic design style provides are generally associated with the performance of logic gates. There is no inherent speed advantage in NDL designs that relates to data transmission, which, like traditional dynamic logic, is dominated by an RC delay. However, transmitting data using dynamic signals in dynamic logic designs does consume more power than transmitting data in a static design, again because of the higher transistor switch factor required to move dynamic signals. Also, there is a routing burden for complimentary dynamic logic, as at least two wires are needed to transmit a single bit of data.
The present invention provides an apparatus and method that FAST14 designers can utilize in connection with the static storage elements disclosed in the Static Storage Element Patent to reduce the power consumption associated with data transmission in NDL designs.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus for the static transmission of FAST14 logic's 1-of-N signals. A static output signal is generated using a static storage element and transmitted to a NDL gate over a transmission path that is characterized by a user-specified multi-cycle timing constraint that is interpreted by the compiler of one or more development tools to create appropriate verification tests of the apparatus. The multi-cycle timing constraint may be a pragma that is interpreted by the compiler of a timing analysis tool such as PATHMILL to create statements that check the set-up and hold times of the static signal relative to the rising edge or falling edge of user-specified clock signal pulses. The same pragma is interpreted by the compiler of a functional verification tool such as VIS to create statements that test the behavior of the apparatus during the clock signal pulses other than the user-specified clock signal pulses tested by the timing analysis tool.
As a result of the setup and hold times associated with static signals that are inputs to dynamic gates, the static output signal may be required to hold its value for at least two successive clock cycles. To achieve higher data throughput, the present invention may include a dynamic mux that, during each clock cycle, selects either the static output signal or a second static output signal that also holds its value for at least two successive clock cycles. If the first and second static output signals are allowed to
Blomgren James S.
Boehm Fritz A.
Potter Laura A.
Potter Terence M.
Booth Matthew J.
Booth & Wright LLP
Intrinsity, Inc.
Tan Vibol
Wright Karen S.
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