Static timing slacks analysis and modification

Details Static timing slacks analysis and modification Static timing slacks analysis and modification

2008-07-22

2008-07-22

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07404163

ABSTRACT:
A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

REFERENCES:
patent: 7142991 (2006-11-01), Hathaway et al.
patent: 7174523 (2007-02-01), Engel et al.
patent: 7278120 (2007-10-01), Rahmat et al.

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