Static timing and risk analysis tool

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000

Reexamination Certificate

active

11028403

ABSTRACT:
A system and method for evaluating multiple corner case static timing analyses. For each node within the analysis, the variability and margin of the node is used to create a risk factor that is used to identify nodes for further analysis. In some cases, a subset of nodes may be selected for static timing analysis with several additional corner cases. The variability of the node may be determined by the difference between the maximum and minimum value of the node between corner case analyses. The margin may be determined by the difference between the actual timing and the required timing. Various ratios using variability and margin may be used to identify those nodes on which to perform further analysis.

REFERENCES:
patent: 6427226 (2002-07-01), Mallick et al.
patent: 6442741 (2002-08-01), Schultz
patent: 6658635 (2003-12-01), Tanimoto
patent: 6851098 (2005-02-01), Schultz
patent: 7032191 (2006-04-01), Malekkhosravi et al.
patent: 2005/0193353 (2005-09-01), Malekkhosravi et al.
patent: 2005/0256921 (2005-11-01), Amekawa et al.

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