Static timing analysis with simulations on critical path...

Details Static timing analysis with simulations on critical path... Static timing analysis with simulations on critical path...

2000-02-10

2003-04-22

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

06553549

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an architecture and/or method for static timing analysis generally and, more particularly, to static timing analysis with simulations on critical path netlists generated by static timing analysis tools.
BACKGROUND OF THE INVENTION
Conventional simulation tools (e.g., Pathmill, a software tool available from Synopsys) are used for static timing analysis. However, such tools cannot analyze multiple input switching in the static mode. The resulting critical path netlist ties off (i) n-channel gates in NAND gates and (ii) p-channel gates in NOR gates to VDD and VSS, respectively. Conventional tools implement additional separate tools for such analysis. However, such additional tools have an extra cost and provide less than desirable accuracy and have capacity constraints, especially as the number of stages increases.
Since conventional static timing analysis tools cannot analyze multiple input switching in static mode, analysis results of such tools are not accurate.
FIG. 1
illustrates a netlist with capacity to handle larger circuits, where circuit simulators such as HSPICE (e.g., a simulator available from Avant!) will either not run or take much longer and require more expensive and complex hardware.
FIG. 2
illustrates a critical path netlist implemented to run more accurate hspice simulations. However, the critical path netlist of
FIG. 2
still has only one input switching case. The other inputs of the NANDs (or NORs) gates are tied to VCC and VSS, appropriately. Analysis errors increase for larger numbers of sequential stages of logic gates. Deviation of the analysis results increase as the number of sequential stages increase.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a plurality of gates and a plurality of control circuits. The plurality of gates may each have an output connected to an input of a next gate of the plurality of gates. The plurality of control circuits may be connected to a second input of one or more gates of the plurality of gates. The plurality of control circuits may simulate switching.
The objects, features and advantages of the present invention include providing a method and/or architecture for static timing analysis that may (i) analyze multiple input switching cases in static mode, (ii) provide an accurate netlist analysis, (iii) provide a critical path netlist analysis and/or (iv) handle larger circuits.


REFERENCES:
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patent: 6075932 (2000-06-01), Khouja et al.
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patent: 6236613 (2001-05-01), Ooshi
Greco et al., “Control of the switching transients of IGBTs series strings by high-performance drive units”, 1999, IEEE, pp. 197-203 vol. 1.

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