Static timing analysis validation tool for ASIC cores

Details Static timing analysis validation tool for ASIC cores Static timing analysis validation tool for ASIC cores

2001-04-16

2003-07-22

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06598213

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to design tools for application-specific integrated circuit integrated circuit (ASIC) design. More specifically, but without limitation thereto, the present invention relates to a method for characterizing the worst case performance of an ASIC core due to capacitive coupling between the ASIC core and metal interconnect layers.
A core is a pre-defined group of circuit elements and modules connected together to perform a specific function. Cores are provided as part of an ASIC design technology library that is used by a circuit designer to implement a specific circuit design. The operation of a core may be significantly influenced by its environment, especially by capacitive coupling between the core and interconnects that are routed in metal layers above the core.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the problems above as well as other problems by providing a method of characterizing worst case timing performance for an ASIC core that may be included in a library for use with logic design tools.
In one embodiment, the present invention may be characterized as a method of characterizing worst case timing performance that includes the steps of receiving as input a netlist of a core, performing a parasitic extraction on the netlist to generate a first standard parasitic extraction format file for a first assumed top metal layer over the core, performing a parasitic extraction on the netlist to generate a second standard parasitic extraction format file for a second assumed top metal layer over the core, calculating a minimum timing value from each delay arc of the first standard parasitic extraction format file, calculating a maximum timing value from each delay arc of the second standard parasitic extraction format file, and merging the minimum timing value calculated from each delay arc of the first standard parasitic extraction format file and the maximum timing value of each delay arc calculated from the second standard parasitic extraction format file to generate an output file.
In another embodiment, the present invention may be characterized as a method of characterizing worst case timing performance that includes the steps of receiving as input a netlist of a core, performing a parasitic extraction on the netlist to generate a first standard parasitic extraction format file for a first assumed top metal layer over the core, performing a parasitic extraction on the netlist to generate a second standard parasitic extraction format file for a second assumed top metal layer over the core, performing a delay calculation on the first standard parasitic extraction format file to generate a first standard delay format file, performing a delay calculation on the second standard parasitic extraction format file to generate a second standard delay format file, selecting a longest timing value for each delay arc from the first standard delay format file, inserting the longest timing value for each delay arc from the first standard delay format file into a maximum timing value of each corresponding delay arc of an output file, selecting a shortest timing value for each delay arc from the second standard delay format file, inserting the shortest timing value for each delay arc from the second standard delay format file into a minimum timing value of each corresponding delay arc of the output file, and generating as output the minimum timing value and the maximum timing value of each corresponding delay arc of the output file in standard delay format.
In yet another embodiment, the present invention may be characterized as a computer program product that includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform the following functions: receiving as input a netlist of a core, performing a parasitic extraction on the netlist to generate a first standard parasitic extraction format file for a first assumed top metal layer over the core, performing a parasitic extraction on the netlist to generate a second standard parasitic extraction format file for a second assumed top metal layer over the core, selecting a longest timing value for each delay arc from the first standard delay format file, inserting the longest timing value for each delay arc from the first standard delay format file into a maximum timing value of each corresponding delay arc of an output file, selecting a shortest timing value for each delay arc from the second standard delay format file, inserting the shortest timing value for each delay arc from the second standard delay format file into a minimum timing value of each corresponding delay arc of the output file, and generating as output the minimum timing value and the maximum timing value of each corresponding delay arc of the output file in standard delay format.


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