Static timing analysis of digital electronic circuits using...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C703S002000, C703S015000, C703S019000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C713S500000

Reexamination Certificate

active

06237127

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the static timing analysis of digital electronic circuits. More specifically, the present invention relates to analyzing certain paths of a circuit under non-default timing constraints known as exceptions.
BACKGROUND OF THE INVENTION
To tackle the increasing complexity of digital electronic circuits, designers need faster and more accurate methods for statically analyzing the timing of such circuits, particularly in light of ever-shrinking product development times.
The complexity of designing such circuits is often handled by expressing the design in a high-level hardware description language (HLHDL).
HLHDLs allow the designer to save design time by permitting him or her to express the desired functionality at the register transfer level (RTL) of abstraction or higher. The high-level HDL description is then converted into an actual circuit through a process, well known to those of ordinary skill in the art as “synthesis,” involving translation and optimization.
HLHDLs describe, directly or indirectly, the two main kinds of circuit entities of an RTL circuit description: i) state devices or sequential logic which store data upon application of a clock signal, and ii) combinational logic. The state devices typically act as either: i) an interface between conceptually distinct circuit systems, or ii) storage for the results of functional evaluation performed by the combinational logic.
In the process of digital circuit design, static timing analysis is often useful in order to verify that the design produced, in addition to being functionally correct, will perform correctly at the target clock speeds. For similar reasons, it would be useful to apply, as efficiently as possible, static timing analysis to the synthesis process.
SUMMARY OF THE INVENTION
The present invention may be used in the hardware synthesis environment known as the “Design Compiler shell” produced by Synopsys, Inc., of Mountain View, Calif.
Exceptions can be a very powerful tool for guiding the Design Compiler portion of the Design Compiler shell towards the synthesis of a more efficient final circuit netlist. This is because exceptions allow the designer, for example, to inform Design Compiler that despite default timing constraints, certain paths through the circuit are subject to less demanding performance requirements in the context of the design's actual application. Exceptions are also useful for further analysis, by the designer, of the final circuit netlist produced by Design Compiler.
Exceptions are specified by the circuit designer as individual syntactic units called “exception statements” which are comprised of a “timing alteration” and a “path specification.” The timing alteration instructs the timing analyzer how to alter the default timing constraints for paths through the circuit to be analyzed which satisfy the path specification. The path specification consists of one or more “path specifiers,” with each path specifier taking an “argument.” In order for a path specification to be satisfied, each argument of each of its path specifiers must be satisfied.
The static timing analysis of the present invention is performed upon units of the circuit, referred to as “sections”, which comprise a set of “launch” flip flops, non-cyclic combinational circuitry and a set of “capture” flip flops.
The section to be analyzed is represented by a netlist of flip flops and combinational logic connected together, at their pins, by wire objects.
The tag-based static timing analysis of the present invention, implementing exceptions statements, is performed in four main steps: preprocessing, pin-labeling, RF timing table propagation and relative constraint analysis. Each of these four steps can be accomplished in one of two main ways, depending upon how exception statements are to be implemented.
For a first-way of implementing exception statements, these four steps are referred to as: first-way preprocessing, first-way pin-labeling, first-way modified RF timing table propagation and first-way modified relative constraint analysis.
For a second-way of implementing exception statements, these four steps are referred to as: second-way preprocessing, second-way pin-labeling, second-way modified RF timing table propagation and second-way modified relative constraint analysis.
Preprocessing accepts the exception statements written by the circuit designer and converts them into a set of preprocessed exceptions statements which has their path specifications expressed in a certain standard form. Both first-way and second-way preprocessing convert the path specification of an exception statement into a form expressed literally in terms of pins of the circuit description netlist. For the first-way of implementing exception statements, each pin is specified independently in the path specifications by being its own path specifier argument. For the second-way of implementing exception statements, a group of pins may be specified as being logically equivalent, in terms of their ability to satisfy a path specification, by their being grouped into an OR-type path specifier argument.
In pin-labeling, the pins of the circuit network, specifically referred to by the preprocessed exception statements, are marked to indicate their being the subject of an exception statement or statements.
In first-way pin labeling, each pin, referred to by a preprocessed exception statement, is marked with an “exception flag.”
In second-way pin labeling, each pin, referred to by a preprocessed exception statement, is given an “argument container” which can contain a collection of “labels.” A label in an argument container is a copy of the “form” in which a preprocessed exception statement has referred to the circuit pin to which the argument container is attached. The purpose of a label is to provide a data item which can be matched against the argument of a path specifier in a preprocessed exception statement. Any form of label, which allows this matching to be accomplished, is suitable. For those path specifier arguments which refer only to a single pin, a label which can match that single-pin reference is put in the argument container. For those path specifier arguments which refer to an OR-expression of several pins, a label which can represents, and can therefore match, the entire OR-expression is put in the argument container.
RF timing table propagation is accomplished as follows.
Delays between the inputs and outputs of either state or combinational devices are represented by “timing arcs.” For the purposes of the set of launch flip flops, we are interested in the delay between a clock edge being applied to the flip flop and a subsequent change, if in fact such a change is caused to occur, at the flip flop's outputs. For the purposes of combinational logic, we are interested in the delay between a change being applied to an input of the logic and a subsequent change, if in fact such a change is caused to occur, at the output.
The RF timing tables propagated are comprised of the following four values: minimum rise time (minRT), maximum rise time (maxRT), minimum fall time (minFT) and maximum fall time (maxFT). RF timing tables each have their own “tag” which, in accordance with the present invention, has two parts: i) a first part which is loaded with a unique identifier for the clock of a launch flip flop, and ii) a second part which can contain a variety of “labels” (described below).
The RF timing tables, for a section of circuitry to be analyzed, are initially created as follows. An RF timing table is created for every output of every launch flip flop. The values for minRT, maxRT, minFT and maxFT of each RF timing table are determined from the timing arc from the flip flop's clock to the output of the flip flop for which the RF timing table is being created. A first part of the tag created for each RF timing table is loaded with an identifier indicating the particular clock driving the clock input of the flip flop for which the RF timing table is being created.

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