Static semiconductor memory with readout inhibit means

Details Static semiconductor memory with readout inhibit means Static semiconductor memory with readout inhibit means

1990-01-22

1991-01-01

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Signals

36518905, 3652335, 36518907, G11C 11413

Patent

active

049823663

ABSTRACT:
A static semiconductor memory device includes a memory cell array including a large number of static memory cells arranged in a matrix fashion, a word decoder, a column decoder, and a data buffer. An address delay buffer is provided for delaying an input address signal by a predetermined delay time and a comparator circuit is provided for comparing the input address signal with the delayed address signal from the address delay buffer, so that even if the input address signal is disturbed by noise, the erroneous data corresponding to the disturbed address signal is not read into the data buffer by means of the output signal of the comparator circuit and is not output from the memory device.

REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4480321 (1984-10-01), Aoyama
patent: 4486883 (1984-12-01), Kanai et al.
patent: 4573147 (1986-02-01), Aoyama et al.
Mackie et al., "Echo Check Circuit", IBM Technical Disclosure Bulletin, vol. 11, No. 2, July, 1968, pp. 197-198.
Burke, "Diagnostic Mode", IBM Technical Disclosure Bulletin, vol. 13, No. 3, Aug., 1970, pp. 655-656.

Affiliated with

Also associated with

Rating

Static semiconductor memory with readout inhibit means does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Static semiconductor memory with readout inhibit means, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Static semiconductor memory with readout inhibit means will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2001842