Static semiconductor memory with a dummy call and a write...

Details Static semiconductor memory with a dummy call and a write... Static semiconductor memory with a dummy call and a write...

2011-07-12

2011-07-12

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000, C365S189160, C365S202000, C365S210100, C365S210110, C365S210120, C365S210130, C365S233100, C365S233160

Reexamination Certificate

active

07978503

ABSTRACT:
A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of the memory cell, the timing of ending the write assist operation is determined by a voltage control circuit based on information about the dummy memory cell. For example, the voltage control circuit performs, in a data write operation in the memory cell, the write assist operation of decreasing the voltage of a source power supply allocated to P-channel MOS load transistors using a pull-down transistor. Thereafter, at the time when completion of the data write operation in the dummy memory cell is detected, the voltage control circuit ends the write assist operation and restores the voltage of the source power supply to the original level using a pull-up transistor.

REFERENCES:
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patent: 6316812 (2001-11-01), Nagoaka
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patent: 6862227 (2005-03-01), Yamaoka et al.
patent: 6977834 (2005-12-01), Onizawa et al.
patent: 6999367 (2006-02-01), Yamagami
patent: 2002-42476 (2002-02-01), None
M. Yamaoka et al., “Low-Power Embedded SRAM Modules with Expanded Margins for Writing”, ISSCC Digest of Technical Papers, Feb. 9, 2005, pp. 480-481 & 611.

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