Static semiconductor memory device operating at high speed under

Details Static semiconductor memory device operating at high speed under Static semiconductor memory device operating at high speed under

1998-05-05

2000-05-23

Nelms, David

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518908, G11C 1604

Patent

active

060672560

ABSTRACT:
A bit line load element for reducing a bit line amplitude during data reading is formed of p- and n-channel MOS transistors connected in parallel. When a word line is driven to the selected state, the p-channel MOS transistor is held off. In the data write operation, both the n- and p-channel MOS transistors are turned off. Even under a low power supply voltage, a sufficiently large bit line amplitude can be produced without an influence by a size of the bit line load element. By deactivating the bit line load element in the data write operation, it is possible to prevent generation of a DC current during data writing.

REFERENCES:
patent: 4730279 (1988-03-01), Ohtani
patent: 4751680 (1988-06-01), Wang et al.
patent: 5666324 (1997-09-01), Kosugi et al.
patent: 5724292 (1998-03-01), Wada

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