Static semiconductor memory device including a bipolar transisto

Details Static semiconductor memory device including a bipolar transisto Static semiconductor memory device including a bipolar transisto

1996-10-21

1998-08-11

Hoang, Huan

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365177, 257205, 257478, G11C 1100

Patent

active

057936706

ABSTRACT:
A memory cell includes first and second driver transistors, first and second access transistors and first and second load elements, and in addition, first and second bipolar transistors. Accordingly, static noise margin is enlarged. The first bipolar transistor has its emitter formed in one of the source/drain regions of the first access transistor. The collector of the first bipolar transistor is the backgate terminal of the first access transistor. One of the source/drain regions of the first access transistor functions as the base of the first bipolar transistor. The same applies to the second bipolar transistor and the second access transistor. As the memory cell is structured in the above described manner, lower power supply potential can be used without the problem of latch up or increased area.

REFERENCES:
patent: 4839862 (1989-06-01), Shiba et al.
patent: 4868628 (1989-09-01), Simmons
patent: 4903090 (1990-02-01), Yokoyama
patent: 5363325 (1994-11-01), Sumouchi et al.
patent: 5483483 (1996-01-01), Choi et al.
Tomohisa Wada, et al: "A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon" IEEE Journal of Solid-State Circuits, vol. SC22, No. 5, Oct. 1987, pp. 727-732.
Katsuro Sasaki, et al: "A 9-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1219-1225.

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