Static semiconductor memory device having data lines in parallel

Static information storage and retrieval – Systems using particular element – Flip-flop

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365 51, 365 63, G11C 1100

Patent

active

060090103

ABSTRACT:
In a static memory cell including two load resistors connected to a power supply line, two cross-coupled drive transistors connected between the load resistors and two ground lines and two transfer transistors connected between the load resistors and two data lines, the data lines are in parallel with and do not cross over the power supply line and the ground lines.

REFERENCES:
patent: 5724293 (1998-03-01), Tomishima et al.
patent: 5815454 (1998-09-01), Tomishima et al.
patent: 5867440 (1999-02-01), Hidaka
Sekiyama et al., "A 1-V Operating 256-kb Full-CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 27, No. 5, May 1992, pp. 776-782.
Horiba et al., "A Symmetric Diagonal Driver Transistor SRAM Cell . . . Stable Low Voltage Operation", 1996 Symposium on VLSI Technology Digest of Technical Papers, 1996, pp. 144-145.

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