Static semiconductor memory device having circuitry for lowering

Details Static semiconductor memory device having circuitry for lowering Static semiconductor memory device having circuitry for lowering

1995-03-10

1996-05-07

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365194, 36518901, G11C 700

Patent

active

055153267

ABSTRACT:
A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

REFERENCES:
patent: 4337523 (1982-06-01), Hotta et al.
patent: 4982372 (1991-01-01), Matsuo
patent: 5262919 (1993-11-01), Kuriyama et al.
"A 12-NS ECL I/O 256KX1-Bit SRAM using a 1 .mu.M BiCMOS Technology", Robert Kertis et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
"An 8-NS 256K ECL SRAM with CMOS Memory Array and Battery Backup Capability", Hiep Van Tran et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
"A 7-NS 1-MB BiCMOS ECL SRAM with Shift Redundancy", Atsushi Ohba et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.

Affiliated with

Also associated with

Rating

Static semiconductor memory device having circuitry for lowering does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Static semiconductor memory device having circuitry for lowering, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Static semiconductor memory device having circuitry for lowering will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1232699