Static semiconductor memory device having circuitry for enlargin

Details Static semiconductor memory device having circuitry for enlargin Static semiconductor memory device having circuitry for enlargin

1995-03-10

1996-04-09

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

365203, 36518911, G11C 700

Patent

active

055068057

ABSTRACT:
A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

REFERENCES:
patent: 4665507 (1987-05-01), Gondou et al.
patent: 4982372 (1991-01-01), Matsuo
patent: 5297090 (1994-03-01), McClure
"A 12-NS ECL I/O 256KX1-Bit SRAM Using A 1.mu.MBICMOSTechnology", Robert Kertis et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
"An 8-NS 256K ECL SRAM With CMOS Memory Array And Battery Backup Capability", Hiep Van Tran et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
"A 7-NS 1-MB BICMOS ECL SRAM With Shift Redundancy", Atsushi Ohba et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.

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