Static semiconductor memory device capable of enhancing...

Details Static semiconductor memory device capable of enhancing... Static semiconductor memory device capable of enhancing...

1998-02-27

2001-01-23

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C257S903000, C257S904000

Reexamination Certificate

active

06178110

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static semiconductor memory device, and more particularly, to the improvement of a static random access memory (SRAM) cell.
2. Description of the Related Art
A prior art SRAM cell is constructed by a flip-flop formed by cross-coupled first and second inverters and transfer transistors connected between first and second nodes of the flip-flop and data lines. That is, the first inverter is formed by a first load resistor between a power supply line and the first node and a drive MOS transistor between the first node and a ground line. Similarly, the second inverter is formed by a second load resistor element between the power supply line and the second node and a second drive MOS transistor between the second node and the ground line. In this SRAM cell, in order to increase the access speed, a salidation technology has been adopted. For example, the gate electrodes are constructed by a double configuration made of polycrystalline silicon and metal silicide. This will be explained later in detail.
In the above-described prior art SRAM cell however, since the load resistors are formed on the same plane as the gates of the drive transistors and the transfer transistors, the area of the SRAM cell is increased, which is disadvantageous in terms of integration.
If the load resistor is formed over the gates of the drive transistors, a parasitic resistance between the gate of the drive transistor and the source of the transfer transistor at the node is increased, thus remarkably decreasing the access speed of the SRAM cell. This also will be explained later in detail.
SUMMARY OF THE INVENTION
It is an object of the invention to enhance the access speed of an SRAM cell as well as improve the integration thereof.
According to the present invention, in a static memory cell including first and second drive MOS transistors, first and second MOS transfer transistors and first and second load elements, the drain of the first drive MOS transistor and the source of the first transfer MOS transistor are formed by a first impurity region in a semiconductor substrate, and the drain of the second drive MOS transistor and the source of the second transfer MOS transistor are formed by a second impurity region in the semiconductor substrate. Also, a first metal silicide layer is formed on the first impurity region and the gate of the second drive MOS transistor, and a second metal silicide layer is formed on the second impurity region and the gate of the drive MOS transistor. Further, the first and second load elements are formed on the first and second metal silicide layers, respectively.
Thus, since the load elements are formed on a different plane from that of the transfer transistors and the drive transistors, the size of the SRAM cell can be reduced. Also, since the metal silicide layers are formed at the contact nodes, the parasitic resistance thereof can be reduced, thus increasing the access speed of the SRAM cell.


REFERENCES:
patent: 5331170 (1994-07-01), Hayashi
patent: 5535155 (1996-07-01), Abe
patent: 5734179 (1998-03-01), Chang et al.
patent: 5774393 (1998-06-01), Kuriyama
patent: 4-320371 (1992-11-01), None
patent: 7-202032 (1995-08-01), None
patent: 8-274190 (1996-10-01), None

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