Static semiconductor memory device capable of accurately...

Details Static semiconductor memory device capable of accurately... Static semiconductor memory device capable of accurately...

2001-07-26

2003-03-18

Tran, Mike (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S233500

Reexamination Certificate

active

06535441

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static semiconductor memory device capable of detecting a failure in a standby mode.
2. Description of the Background Art
Referring to
FIG. 23
, a static memory cell (SRAM (Static Random Access Memory))
10
has p-channel MOS transistors
1
and
2
, n-channel MOS transistors
3
to
6
, and storage nodes N
1
and N
2
. The p-channel MOS transistor
1
is connected between a power source node
35
and the storage node N
1
, and the p-channel MOS transistor
2
is connected between the power source node
35
and the storage node N
2
. The n-channel MOS transistor
3
is connected between the storage node N
1
and a ground node
36
, and the n-channel MOS transistor
4
is connected between the storage node N
2
and the ground node
36
. A voltage on the storage node N
1
is applied to the gate terminals of the p-channel MOS transistor
2
and the n-channel MOS transistor
4
, and a voltage on the storage node N
2
is applied to the gate terminals of the p-channel MOS transistor
1
and the n-channel MOS transistor
3
. The n-channel MOS transistor
5
is connected between the storage node N
1
and a bit line BL, and the n-channel MOS transistor
6
is connected between the storage node N
2
and a bit line /BL. The n-channel MOS transistors
5
and
6
are turned on/off by a word line (WL).
When the potential on the storage node N
1
is at the H (logical high) level and that on the storage node N
2
is at the L (logical low) level, the memory cell
10
stores data “1”. When the potential on the storage node N
1
is at the L level and that on the storage node N
2
is at the H level, the memory cell
10
stores data “0”.
When the data “1” is written in the memory cell
10
, the potential on the bit line BL is held H level and the potential on the bit line /BL is held L level. When the word line (WL) is activated, the n-channel MOS transistors
5
and
6
are turned on, the potential on the storage node N
1
goes H level which is the same as the potential on the bit line BL, and the potential on the storage node N
2
goes L level which is the same as the potential on the bit line /BL. Accordingly, the p-channel MOS transistor
1
is turned on and the n-channel MOS transistor
3
is turned off, so that the potential on the storage node N
1
is latched at the H level. The p-channel MOS transistor
2
is turned off and the n-channel MOS transistor
4
is turned off, so that the potential on the storage node N
2
is latched at the L level. After that, when the word line (WL) is inactivated, the n-channel MOS transistors
5
and
6
are turned off, the potential on the storage node N
1
is held H level, the potential on the storage node N
2
is held L level, and the data “1” is written in the memory cell
10
. When the data “0” is written in the memory cell
10
, the potential on the bit line BL is held L level and the potential on the bit line /BL is held H level. The same writing operation as that in the case where the data “1” is written is performed.
In the case of reading the data “1” from the memory cell
10
, by making the word line (WL) active, the n-channel MOS transistors
5
and
6
are turned on to make the memory cell
10
active. Since the potential on the storage node N
1
is H level, the p-channel MOS transistor
2
is turned off, the n-channel MOS transistor
4
is turned on, a current flows from the bit line /BL to the ground node
36
via the n-channel MOS transistors
4
and
6
, and the potential on the bit line /BL goes L level. The p-channel MOS transistor
1
is turned on and the n-channel MOS transistor
3
is turned off, so that the current flows from the power source node
35
to the bit line BL via the p-channel MOS transistor
1
and the n-channel MOS transistor
5
, and the potential on the bit line BL goes H level.
The operation in the case of reading the data “0” from the memory cell
10
is the same as that in the case of reading the data “1”.
As obviously understood from
FIG. 23
, the memory cell
10
is what is called a full CMOS (Complementary MOS) type SRAM constructed by six MOS transistors. Since a memory cell of this type is constructed only by MOS transistors, a path through which a direct current flows does not exist in a state where data is held. Only a very slight amount of current (the order of 10
−15
A) such as a sub-threshold current or junction leak current flows. In a memory cell of this type, therefore, a standby current of about 0.1 &mgr;A can be realized.
An operation test is conducted on the memory cell
10
before shipment. The operation test includes a test of writing/reading data to/from the memory cell
10
and a retention test. The writing/reading test is a test for determining whether the memory cell is good or not by writing predetermined data to the memory cell
10
, reading the written data, and checking whether the read data coincides with the written data or not. The retention test is conducted after the writing/reading test, by holding a voltage to be applied to the memory cell
10
so as to be lower than an external source voltage in normal operation, after elapse of a predetermined time, reading the data from the memory cell
10
, and checking whether the written data is retained or not, thereby determining whether the memory cell is good or not.
FIG. 24
shows the profile of a voltage applied to the memory cell
10
at the time of an operation test. During a period T
1
, 3.3V as an external power source voltage is applied to the memory cell
10
and the writing/reading test is carried out. During a period T
2
, a voltage applied to the memory cell
10
is lowered from 3.3V to a range from 1.0 to 1.5V and held. After that, during a period T
3
, 3.3V as the external source voltage is applied to the memory cell
10
and data is read.
When a foreign matter is adhered to the memory cell
10
, however, as shown in
FIG. 23
, a leak current
91
flows between the power source node
35
and the storage node N
2
. When the storage node N
1
is held H level and the storage node N
2
is held L level, the p-channel MOS transistor
2
is turned off and the n-channel MOS transistor
4
is turned on. Consequently, an ON-state current
92
flows from the storage node N
2
via the n-channel MOS transistor
4
to the ground node
36
. In this case, even if the leak current
91
of a few &mgr;A flows due to a foreign matter, under normal operation conditions of applying an external source voltage of about 3.3V to memory cells, the ON-state current is 10 &mgr;A or larger, and the SRAM operates normally. However, a current in the standby mode is abnormal. In order to detect a memory cell having an abnormal current in a standby mode by an operation test, it is necessary to decrease the ON-state current of the n-channel MOS transistor
4
shown in
FIG. 23
to 1 &mgr;A or lower. In order to set the ON-state current of the n-channel MOS transistor
4
to 1 &mgr;A or lower, a voltage applied to the power source node
35
of the memory cell
10
has to be set to about a threshold voltage Vth of the n-channel MOS transistor
4
at the time of the retention test.
It is, however, difficult to apply the voltage which is about the threshold voltage Vth from the outside to the memory cell due to an influence of temperature fluctuation or the like, and there is a problem such that a memory cell having an abnormal current in a standby mode due to a leak current cannot be detected.
SUMMARY OF THE INVENTION
An object of the invention is, therefore, to provide a static semiconductor memory device capable of detecting a memory cell having an abnormal current in a standby mode by an operation test.
A static semiconductor memory device according to the invention has: a plurality of static memory cells provided between a first node and a second node; a control terminal for receiving a control signal; a test mode signal generating circuit generating an activated test mode signal when a voltage level of the control signal is equal to or higher than a predetermined l

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