Static semiconductor memory device and fabricating method...

Details Static semiconductor memory device and fabricating method... Static semiconductor memory device and fabricating method...

2000-03-27

2001-09-11

Elms, Richard (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000

Reexamination Certificate

active

06288926

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static semiconductor memory device, and more particularly to a static semiconductor memory device which can prevent operational failure caused by increase of voltage at a ground voltage line at the time of high speed and low voltage operation.
2. Descriptions of the Prior Art
Memory cells of the static semiconductor memory device can be classified into a CMOS type comprising six transistors and a high-resistance loading type comprising two resistors and four transistors.
The high-resistance loading type memory cell is advantageous in reducing the chip area, but disadvantageous in increasing power consumption. The CMOS type memory cell is advantageous in reducing power consumption, but advantageous in increasing the chip area.
In a conventional static semiconductor memory device, the high-resistance loading type memory cell is used for constructing memory cell arrays to reduce the chip area.
However, since the static semiconductor memory device operates at high speed and at low voltage, the CMOS type memory cell is inevitably used to reduce power consumption.
A technique disclosed in U.S. Pat. No. 5,654,915 entitled “Six (6) Bulk Transistor Static Memory Cell Using Split Word line Architecture” discloses the layout of a CMOS type memory cell to reduce the chip area.
FIG. 1
illustrates the circuit and signal line arrangement of the CMOS type of memory cells disclosed in U.S. Pat. No. 5,654,915.
The CMOS type of memory cell is constructed with two (2) loading transistors P
1
, P
2
; two access transistors N
1
, N
4
; and two pulldown transistors N
2
, N
3
. The two loading transistors P
1
, P
2
are vertically arranged in a rectangular shape. Also, the access transistors N
1
, N
4
and two pulldown transistors N
2
, N
3
are vertically arranged in a rectangular shape.
A split word line WL extends in a horizontal direction, and a supply voltage line VCC, a ground voltage line VSS and a pair of bit lines BL, BLB extends in a vertical direction.
The operation of the CMOS type of memory cells thus constructed will be described below.
A high-level signal is applied to a word line WL to turn on the two access transistors N
1
, N
4
. A high-level signal is applied to the bit line BL. A low level signal is applied to the inverted bit line BLB. The high and low level signals are transmitted to the drains of the two access transistors N
1
, N
4
. The loading transistor P
1
and the pulldown transistor N
3
turn on. The high and low level signals are further transmitted to the drains of the access transistors N
1
, N
4
. In other words, the signals transmitted through the access transistors N
1
, N
4
are latched by cross-coupled transistors P
1
, P
2
and pulldown transistors N
2
, N
3
. The complementary signals present on the bit lines BL, BLB thus are stored in the memory cell.
FIG. 2
illustrates the layout of the memory cell shown in
FIG. 1
, including an active area
10
constructed with loading transistors and another active area
12
constructed with access transistors and pulldown transistors. Furthermore, reference symbols P
1
d
, P
2
d
, N
1
d
, N
2
d
, N
3
d
, N
4
d
indicate drains of the transistors, reference symbols, P
1
s
, P
2
s
, N
1
s
, N
2
s
, N
3
s
, N
4
s
indicate sources of the transistors, and P
1
g
, P
2
g
, N
1
g
, N
2
g
, N
3
g
, N
4
g
indicate gates of the transistors.
Above mentioned U.S. Pat. No. 5,654,915 discloses the same layout of memory cell as shown in
FIG. 2
to improve the structure of the conventional CMOS type of memory cell.
However, there is a problem in the CMOS type memory cell shown in FIG.
2
. In detail, if the ground voltage line gets longer to increase its voltage, the margin between the supply voltage level and the ground voltage level decreases during low-voltage operation, thereby potentially causing operational failure in processing the data latched by the memory cell.
Accordingly, a need arises to correct such a problem in any static semiconductor memory device constructed with the conventional CMOS type memory cell as well as in the static semiconductor memory device constructed in the layout shown in
FIGS. 1 and 2
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a static semiconductor memory device which can prevent an operational failure by securing a margin between supply voltage level and ground voltage level of the data latched at the memory cells in spite of high-resistance formed at the ground voltage line at the time of low voltage operations.
In order to accomplish the aforementioned object, a semiconductor memory device of the present invention is comprised of a plurality of word lines arranged in the horizontal direction; a plurality of bit lines arranged in perpendicular to the plurality of word lines; a plurality of supply voltage lines arranged in the same direction as the plurality of bit lines; a plurality of first ground voltage lines arranged in the same direction as the plurality of bit lines; a plurality of second ground voltage lines arranged in the same direction as the plurality of word lines; and the plurality of memory cells connected between the plurality of word lines and the plurality of bit lines.
In an alternative embodiment, a static semiconductor memory device of the present invention is comprised of: a plurality of word lines arranged in the horizontal direction; a plurality of pairs of bit lines each comprising a bit line and an inverted bit line and arranged in perpendicular to the plurality of word lines; a plurality of supply voltage lines arranged in the same direction as the plurality of bit lines; a plurality of first ground voltage lines arranged in the same direction as the plurality of bit lines; a plurality of second ground voltage lines arranged in the same direction as the plurality of word lines; and a plurality of static memory cells connected between the plurality of word lines and the plurality of pairs of bit lines. Here, the static memory cell is comprised of first and second access transistors respectively connected to a bit line and an inverted bit line of the pair of bit lines having a control electrode connected to one of the plurality of word lines. First loading and pulldown transistors are connected between the supply voltage lines and the first and second ground voltage lines to invert the signals transmitted from the first access transistor and, transmit the inverted signals to the second access transistor. Second loading and pulldown transistors are connected between the supply voltage lines and the first and second ground voltage lines to invert the signals transmitted from the second access transistor and, further, transmit the inverted signals to the first access transistor.


REFERENCES:
patent: 5293559 (1994-03-01), Kim et al.
patent: 5325336 (1994-06-01), Tomishima et al.
patent: 5867440 (1999-02-01), Hidaka

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