Static Semiconductor memory device

Details Static Semiconductor memory device Static Semiconductor memory device

1997-01-13

1998-03-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Differential sensing

365154, 36518901, 365205, G11C 702

Patent

active

057242925

ABSTRACT:
Sense circuits are provided correspondingly to bit line pairs provided corresponding to memory cell columns, respectively. The sense circuit senses, amplifies and latches storage data of the selected memory cell, and information latched by the sense amplifier is rewritten into the selected memory cell after selection of the memory cell. Thereby, destruction of storage information of the memory cell is prevented.

REFERENCES:
patent: 5280441 (1994-01-01), Wada et al.
patent: 5434821 (1995-07-01), Watanabe et al.
Shiomi, Toru, et al: "A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped Bit Line Architecture", IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1362-1369.
Wada, Tomohisa, et al: "A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 727-732.
Sasaki, Katsuro, et al: "A 9-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1219-1225.

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