Static semiconductor memory device

Static information storage and retrieval – Systems using particular element – Flip-flop

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365148, G11C 1300

Patent

active

052048349

ABSTRACT:
A plurality of static memory cells 10 each comprising a thin film transistor acting as a load are connected to a power source wiring 12 positioned within a memory cell array. The power source wiring 12 positioned within the memory cell array is connected via a resistor circuit 14 to a power source wiring 13 of a low resistivity, which is positioned outside the memory cell array.

REFERENCES:
patent: 4139786 (1988-02-01), Madland
patent: 4727518 (1988-02-01), Madland
patent: 4805147 (1989-02-01), Yamanaka et al.
Sasaki et al., IEEE Journal of Solid-State Circuits, "A 9-ns 1-Mbit CMOS SRAM," vol. 24, No. 5, Oct. 24, 1989.

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